DesignWare OTP SLP IP

DesignWare One-Time Programmable (OTP) SLP NVM IP is currently available at 180nm, at densities up to 256 Kbits per macro. The OTP SLP NVM IP is designed for very low power applications, such as handheld wireless, remote sensor and implanted medical devices.

DesignWare OTP SLP IP includes several additional features that provide flexibility in customizing the memory operation to target specific applications.

  • Read Mode Options: By default, the OTP SLP IP is read in single-ended mode utilizing one memory cell per logical bit of information. Two additional read modes are provided for enhanced margins and an extra level of data security needed for highly reliable, field-programmable systems: differential mode and redundant mode.
  • Special Operating and Test Modes: The OTP SLP IP has special operating and test modes, such as sense amplifier test mode, word-line test mode and bit-line test mode that can be enabled in order to reliably test the macrocell. Unlike most OTP, testing can be achieved on both the programmed and the un-programmed cells.
  • Mask ROM Option: DesignWare OTP SLP IP can be converted into mask-programmable ROMs with a single mask change. The user has the flexibility to mask program the entire memory or individual portions of the macrocell. This feature gives the customer the ability to mask program a section of the memory while allowing other sections of the memory to be programmed in the field.
  • Optional Power Supply Macro: OTP SLP IP can be combined with an optional power supply macro to allow the customer to program the SLP macrocell in the field after the chip is packaged, eliminating the need for additional power supplies to the chip.

SLP applications include handheld and wireless devices, implanted medical devices, configurable storage, and RFID tags. They are ideal replacements for masked ROM or Flash memory in many applications.

DesignWare NVM IP Complete Solution
DesignWare One-Time Programmable SLP Non-Volatile Memory IP

 

Highlights
  • OTP Features
    • Retention exceeding 10 years (100% duty cycle)
    • Standard CMOS process
    • Highly secure
    • Ultra-low power consumption
    • Multiple read modes
    • Flexible mask ROM option
  • SLP Features
    • Standard CMOS logic process
    • Up to 256 Kbits per macro (multiple macros can be used for higher memory capacity)
    • Up to 128 I/O bits per macrocell
    • Optional Integrated Power Supply (IPS)
    • Ultra-low read power consumption
    • Built-in word-line test mode
    • Built-in bit-line test mode
    • Built-in sense amplifier test mode
    • Built-in cell margin modes for programming verification