Synopsys DesignWare DigRF 3G Controllers and PHY IP Solution

The DesignWare DigRF 3G IP solution is based on the MIPI Alliance DigRF V3.09 specification and consists of DigRF Master and DigRF Slave controllers and a dual mode PHY.

The DigRF 3G (v3.09) is a chip-to-chip communication protocol between the Digital Baseband processor and the Analog Baseband/RF IC, for 3GPP 3G/2.5G (UMTS/EGPRS) Mobile Terminals. The interface reduces the pin count required for baseband processor interfacing RFICs, reduces power consumption and increases interoperability. The DesignWare DigRF 3G IP solution is fully silicon-proven and is designed in multiple end user ICs.

DesignWare 3G DigRF PHY Datasheet
DesignWare DigRF 3G Master Controller Datasheet
DesignWare DigRF 3G Slave Controller Datasheet
DesignWare DigRF v4 Master Controller Datasheet
DesignWare MIPI Complete Solution Datasheet

 

Highlights

Key Features:

  • Silicon-proven Master and Slave Controller IP compliant with DigRF 3G (v3.09) Specification
  • Master controller handles frame construction and serialization in the transmit channel and header decoding and payload processing in the receive channel
  • Basic handset and local diversity with multiplexed interface
  • AMBA┬«-APBTM slave interface for configuration, control and transmission of link commands
  • Silicon-proven dual mode PHY
  • 312Mbps data rate
  • Support sleep and shutdown modes
  • Minimized interface pin-count