Architecture Design Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping Accelerate the creation of your ASIC prototype with a high-speed physical prototyping environment including a comprehensive software flow
Virtual Prototyping Accelerate pre-RTL, embedded software development, hardware/software integration and system validation
Power Electronic Systems Simulate and execute behavioral design, modeling and simulation for power electronics, multi-domain systems and wire harnesses
Helping You Solve Your Toughest IC Design Challenges
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
SoC Integration & Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys' DesignWare® IP for Serial ATA (SATA) Device Controller is compliant to the SATA specification revision 3.2 (backwards compatible to SATA 2.6) supporting 1.5, 3 and 6Gb/sec operation, ensuring scalability and reuse in current and future system-on-chip (SoC) designs. The DesignWare SATA digital device controller offers an integrated DMA with a well-defined, flexible programming model that minimizes software overhead, ensuring maximum operational performance. Sample device firmware for various applications is available, speeding system integration. The solution has passed the SATA-IO Building Block Interoperability Testing, the golden standard of compliance to the SATA Specification.
The DesignWare SATA device core IP configuration offers one-click integration with the DesignWare SATA PHY IP, removing the effort of integrating the digital and mixed-signal portions of the SATA interface design. Reduced gate count and very low power consumption is achieved by utilizing the set of highly configurable options which enable the core to be optimized based on the exact design requirements. The test environment for the DesignWare SATA digital device controller IP includes a number of the DesignWare Verification IP components offering SATA transactions generation, SATA protocol monitoring and AMBA subsystem transaction generation. Verilog-based tests are provided as examples to accelerate system integration.
You can view all Synopsys SATA videos here.DesignWare IP for Data Centers Brochure DesignWare SATA Complete Solution Datasheet
DesignWare® SATA Demonstration See how Global Unichip (GUC) utilized Synopsys' silicon-proven DesignWare® SATA IP in its Solid State Device (SSD) GP5080 platform to demonstrate a netbook boot-up time of less than half a minute. The hardware platform consists of a high-performance 32-bit ARM7 processor, SATA 3Gb/s interface, SLC/MLC NAND Flash management of up to 4 channels, 8 banks with ECC.
Kurt Huang Director of Marketing, Global Unichip Corp.
