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Synopsys DesignWare SATA Device Controller IP
Synopsys' DesignWare® IP for Serial ATA (SATA) Device Controller is compliant with the SATA v3.3 (backwards compatible to SATA 2.6) and PIPE v4.3 specifications supporting 1.5, 3 and 6Gb/sec operation, ensuring scalability and reuse in current and future system-on-chip (SoC) designs. The DesignWare SATA digital device controller offers an integrated DMA with a well-defined, flexible programming model that minimizes software overhead, ensuring maximum operational performance. Sample device firmware for various applications is available, speeding system integration. The solution has passed the SATA-IO Building Block Interoperability Testing, the golden standard of compliance to the SATA Specification.
The DesignWare SATA device core IP configuration offers one-click integration with the DesignWare SATA PHY IP, removing the effort of integrating the digital and mixed-signal portions of the SATA interface design. Reduced gate count and very low power consumption is achieved by utilizing the set of highly configurable options which enable the core to be optimized based on the exact design requirements. The test environment for the DesignWare SATA digital device controller IP includes a number of the DesignWare Verification IP components offering SATA transactions generation, SATA protocol monitoring and AMBA subsystem transaction generation. Verilog-based tests are provided as examples to accelerate system integration. You can view all Synopsys SATA videos here.
DesignWare IP for Data Centers Brochure DesignWare IP Prototyping Kit for SATA 6G Device with PCIe Connection to PC DesignWare IP Prototyping Kits DesignWare SATA Complete Solution Datasheet
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- supports 1.5, 3 & 6 Gbps SATA operations
- Compliant with SATA/eSATA v3.3 and SATA PIPE v4.3 specfications
- Memory data protection and memory address parity protection
- Hardware support for native command queuing (NCQ)
- End-to-end parity data path protection
- End-to-end CRC data (data FISes) protection (in addition to SATA CRC protection)
- Integrated DMA engine with flexible command layer programming model
- Included example command layer firmware
- Optional RX buffer (elasticity buffer) for recovered clock systems
- Optional 8b/10b encoding/decoding
- Optional OOB detection/generation logic
- Data scrambling
- Speed negotiation when TX OOB signaling is enabled
- Full power management features supported
- Supports SATA defined BIST modes
- Native command queuing, streaming, and asynchronous notification
- Configurable AMBA system interface
- Supports disabling of RX and TX clocks during power modes
- Highly configurable PHY interface
- Additional, user defined PHY status and control ports
- SATA-IO Building Block Interoperability Tested