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DesignWare Root Port Controller IP for PCI Express

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The DesignWare® Root Port (RC) Controller IP for PCI Express® (PCIe®) implements a configurable and scalable Root Complex interface for integration into ASICs and FPGAs. The silicon-proven IP is first to pass PCI-SIG compliance, supports the latest PHY Interface for PCIe (PIPE) specification and has been extensively validated with multiple hardware platforms, PHYs and PCIe verification suites, providing designers with a high-quality IP that reduces risk and improves time-to-market.

The synthesizable IP integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing. The IP is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput.

Synopsys offers a portfolio of silicon-proven IP for PCIe consisting of controllers, PHYs, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As the industry standard, Synopsys' solution is in volume production and has been successfully implemented in a wide range of applications.

DesignWare IP for PCI Express Complete Solution Datasheet
DesignWare IP for PCI Express to AMBA AXI3/AXI4 Bridge Datasheet
DesignWare IP for PCI Express to ARM AMBA AHB Interconnect
DesignWare IP Root Port Controller IP for PCI Express Datasheet
DesignWare Z-Core IP for PCI Express Datasheet *Japan Only*
 

  • Designed according to the PCIe 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
  • Supports the latest PIPE specification including variable clock and variable data
  • Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
  • Architecture supports x1, x2, x4, x8, and x16 lanes
  • Available in 32-, 64-, 128-, 256- and 512-bit data path widths for maximum flexibility
  • Optimal on-chip memory utilization
  • Special feature to lower latency
  • Bypass, cut-through and store-and-forward receive queues
  • Embedded DMA for increased performance
  • Full power management support
  • Advanced Error Reporting
  • RAS data protection option for the control, address, data and memories
    • ECC with single-bit correction and double-bit detection on RAMs
    • ECC or parity (even or odd) on datapath
  • Optional debug capabilities, error injection and statistical monitoring
    • Fine-grained error injection
    • Detailed error tracking with statistics capture
    • Detailed internal state tracking with statistics capture
  • Support for Single-Root I/O Virtualization (SR-IOV)
  • ASIC and FPGA support
  • Support for AMBA 4 AXI, 3 AXI and AHB interfaces
PCI Express 1.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)STARsSubscribe
PCI Express 1.0 Root Port - 32 bit (x1,x4), 64-bit (x2,x4,x8)STARsSubscribe
PCI Express 2.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)STARsSubscribe
PCI Express 2.0 Root Port - 32 bit (x1,x4), 64-bit (x2,x4,x8)STARsSubscribe
PCI Express 3.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)STARsSubscribe
PCI Express 3.0 Root Port - 32 bit (x1,x2), 64-bit (x1,x2,x4)STARsSubscribe
PCI Express 4.0 Root Port - 128 bit (x2,x4), 256-bit (x8,x16)STARsSubscribe
PCI Express 4.0 Root Port - 32 bit (x1), 64-bit (x1,x2)STARsSubscribe
PCI Express 4.0 Root Port - 512-bit (x8,x16)STARsSubscribe
IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDPSTARsSubscribe

  Description IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDP
  Name dwipk_pcie3rc_xlnxphy_arc
  Version 1.10a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Download ipk_PCIe3-RC-XLNXPHY_ARC
  Product Code HW0297-0
  
  Description PCI Express 1.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)
  Name dwc_pci_express_rc_gen1_128b_256b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8791-0
  
  Description PCI Express 1.0 Root Port - 32 bit (x1,x4), 64-bit (x2,x4,x8)
  Name dwc_pci_express_rc_gen1_32b_64b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8790-0
  
  Description PCI Express 2.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)
  Name dwc_pci_express_rc_gen2_128b_256b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8799-0
  
  Description PCI Express 2.0 Root Port - 32 bit (x1,x4), 64-bit (x2,x4,x8)
  Name dwc_pci_express_rc_gen2_32b_64b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8798-0
  
  Description PCI Express 3.0 Root Port - 128 bit (x4,x8,x16), 256-bit (x8,x16)
  Name dwc_pci_express_rc_gen3_128b_256b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8807-0
  
  Description PCI Express 3.0 Root Port - 32 bit (x1,x2), 64-bit (x1,x2,x4)
  Name dwc_pci_express_rc_gen3_32b_64b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code 8806-0
  
  Description PCI Express 4.0 Root Port - 128 bit (x2,x4), 256-bit (x8,x16)
  Name dwc_pci_express_rc_gen4_128b_256b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code A712-0
  
  Description PCI Express 4.0 Root Port - 32 bit (x1), 64-bit (x1,x2)
  Name dwc_pci_express_rc_gen4_32b_64b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code A711-0
  
  Description PCI Express 4.0 Root Port - 512-bit (x8,x16)
  Name dwc_pci_express_rc_gen4_512b
  Version 4.70a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_pcie_rc
  Product Code B676-0