DesignWare Root Port Controller IP for PCI Express
The DesignWare® Root Port Controller IP (RC) for PCI Express® (PCIe®) implements a configurable and scalable root port, while supporting all required features of the PCI Express 5.0, 4.0, 3.1, 2.1, 1.1 and PHY Interface for PCI Express (PIPE) specifications. The high-quality, synthesizable IP is available in your choice of datapath widths, PIPE interface widths, operating frequencies, and over 1200 configuration parameters, all working together to enable designers to optimize their applications for size, power, latency and throughput. The DesignWare Root Port Controller IP integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface or an industry-standard AMBA interface, and conservative timing suitable for a wide range of ASIC and FPGA technologies.
The DesignWare Root Port Controller IP has been silicon-validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market. As the industry standard for PCI Express, Synopsys offers a comprehensive IP solution that is in volume production and has been successfully implemented in a wide range of applications.