Ethernet Switching

An Ethernet switch connects a number of Ethernet stations, forming an Ethernet network. Different ports of the switch can be connected to different network segments or individual nodes. The switch learns the MAC addresses observed from frames received through each port and uses this information to forward incoming frames only to the intended destination instead of flooding the network.

The Ethernet switch core is typically integrated into a device allowing for connection with a host processor which operates system management functions and implements higher layer data and protocol processing. The switching function takes care on passing frames on or bypassing the node for traffic not relevant to the local device.

The Ethernet Switch core integrates 10/100/1000 Ethernet MACs allowing direct connection to external PHY devices through standard interfaces like MII or GMII or their pin-reduced serial variants. One dedicated port offers an packet interface e.g. AXI4S for integration into any system environment.

For precise time synchronization applications, the switch and MAC functions support frame timestamping and IEEE 1588v2 correction field updates. A dedicated adjustable timer module is integrated that can be used to provide precise timestamps and system time to the application.

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  • IEEE 802.1/802.3 TSN (Enhancements for Time-Sensitive Networking)
    • Hardware timestamping on line ports with 1-step update support allowing IEEE 1588 or other protocol implementations for clock synchronization
    • Output queues with time based and bandwidth or event based gating and traffic shaping capabilities
    • Cyclic Queueing for deterministic forwarding delay
    • Preemptive MAC function
    • Network Reliability with Monitoring and Policing functions on a per-Stream basis
    • Redundancy functions using frame duplication
  • Industrial Networks (Enhancements for Industrial Networks support)
    • Integrated HUB emulation allowing use with Half-Duplex Powerlink infrastructures
    • Profinet RT and iRT infrastructures with cyclic bandwidth allocation
    • Device Level Ring (DLR) beacon forwarding without need for local processor intervention (CPU load reduction)
    • Cut-Through forwarding