- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+ Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering + Optical Solutions< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST) Mobile Application Security Penetration Testing Managed Static Analysis< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+ Application Security Products + Application Security Services + Resources + Training & Education Blog Support< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries Memory Compliers Duet Packages HPC Design Kit Embedded Test & Repair Non-Volatile Memory< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors Embedded Vision Processors Development Tools Operating Systems Ecosystems ASIP Tools< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive Cloud Computing Financial Services Industrial Controls Systems Healthcare Mobile Devices< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
Software Security Professional Services
Embedded Software Testing Insider Threat Detection Red Teaming Secure Coding Guidelines Software Architecture & Design Thick Client Testing< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM) Maturity Action Plan (MAP) Policies & Standards Security Metrics Software Security-in-a-Box< Software Security
< Software Security
Support
< overview
< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
Community
Community Overview< Community
< Community
< Community
Interoperability
ARC Access HAPS Connect HSPICE Integrator In-Sync System-Level Catalyst TAP-in VC Apps Access< Community
< Community
< Community
< overview
Community
+ Community + SNUG + Partners + Interoperability + Academic Programs + Company Blogs + BSIMM< About Us
< About Us
< About Us
< About Us
< About Us
DesignWare Enterprise Ethernet PCS IP
The DesignWare® Enterprise Ethernet Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3 and consortium specifications for 1G, 10G, 25G, 40G, 50G and 100G Ethernet PCS layers. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) sublayer through a media independent interface.
The DesignWare Enterprise Ethernet PCS IP is designed to support the following derivatives of the PCS layer:
- 100GBASE–LR4 (w/o FEC)
- 100GBASE–ER4 (w/o FEC)
- 100GBASE-SR4 (with RS-FEC)
- 100GBASE-CR4 (with RS-FEC)
- 100GBASE-KR4 (with RS-FEC)
- 50GBASE-R PCS (as per 25G Consortium Chip-2-chip & Chip-to-module CAUI-4
- 40GBASE-R PCS
- 25GBASE-KR, 25GBASE-CR (with RS-FEC, Cl74 FEC)
- 25GBASE-KR-S, 25GBASE-CR-S (with Cl74 FEC)
- 25G BASE-SR (with RS-FEC)
- 25GBASE-R PCS (Specification Revision 1.51 July 2015)
- Chip-2chip & Chip-to-module 25GAUI
- 20GBASE-R PCS
- 10GBASE-R PCS
- 1000BASE-X/SGMII
The DesignWare Enterprise Ethernet PCS IP is verified using state-of-the-art methodologies including the RTL design, verification, hardware verification, and interoperability tests. It can be easily configured with a user-friendly application interface for easy functional and implementation objectives to meet design requirements. Coupled with the configurable DesignWare Enterprise Ethernet MAC IP, the Enterprise Ethernet PCS IP offers easy SoC integration for 1G/10G/25G/40G/50G/100G Ethernet designs.
The DesignWare Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.
DesignWare Enterprise 40G Ethernet PCS Controller IP
Highlights
Products
Downloads and Documentation
- Compliant with IEEE 802.3 and IEEE 802.1 specifications
- Supports IEEE 802.3az-2010 Energy Efficient Ethernet
- Compliant with IEEE 802.3ba-2010 for 40G Ethernet
- Compliant with consortium specifications
- Multiple backplane Ethernet PCS configurations supported
- 40G operations with an XLGMII Interface and 128-bit system interface
- 10G operation with an XGMII interface and 64-bit system interface
- 1G operation with a GMII interface and 32-bit system interface
- Configurable lane control support for 40G modes (KR4 and 40GBASE-R PCS)
- Configurable lane control support for 10G modes (XGXS PCS, KX4, and 10GBASE-X PCS)
- Configurable management interface
- Scrambled idle test pattern generator and checker for 40GBASE-R
- Clock rate compensation of 200ppm (+/- 100 ppm) on the receive MAC interface
- Configurable monitoring, testing, and debugging features
| Description: | Enterprise 40G Ethernet PCS Controller IP |
| Name: | dwc_ether_xlgpcs |
| Version: | 1.00a-lca04 |
| STARs: | Open and/or Closed STARs |
| myDesignWare: | Subscribe for Notifications |
| Product Type: | DesignWare Cores |
| Documentation: |
Hide Documents... Databook DesignWare Cores Enterprise Ethernet PCS DatabookDatasheet DesignWare Enterprise 40G Ethernet PCS Controller IPInstallation Guide DesignWare Cores Enterprise Ethernet PCS Installation GuideRelease Notes DesignWare Cores Enterprise Ethernet PCS Release NotesUser Manual DesignWare Cores Enterprise Ethernet PCS User GuideWhite Paper Virtualizing Cloud Computing With Optimized IP for NFV SoCs |
| Download: | Ether-PCS-40G-MAC |
| Product Code: | 5528-0 |