The Synopsys DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.

Synopsys DDR Complete Solution Datasheet

Highlights

Provides a complete, single vendor DDR3/2 SDRAM interface IP solution, when combined with the Synopsys DDR2/3-Lite PHY IP
Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
Supports data rates of up to 1066Mbps (533 MHz)
Includes a configurable multi-port arbiter with up to 32 host ports using Host Memory Interface (HMI), AMBA AHB or AMBA 3 AXI

Programmable ultra-high priority port (port 0), typically a CPU port

Separate configuration port using Controller Register Interface (CRI) or AMBA 3 AXI with independent clocking
Command re-ordering and scheduling to maximize memory bus utilization

Command reordering between banks based on bank status
Programmable priority arbitration and anti-starvation mechanisms
Configurable per-command priority with up to eight priority levels; also serves as a per-port priority

Automatic scheduling of activate and precharge commands
Automatic scheduling of refreshes
Supports memory interfaces of 8 to 64 bits in 8 bit increments (up to 72 bits with ECC)
Programmable ECC generation, checking, and correction
Support for up to four external memory ranks
Contains basic data training logic for supporting DesignWare DDR2/3-Lite PHYs
Automated Read DQS recognition with Dynamic Drift Compensation
Programmable timing parameters support DDR3/DDR2/gDDR2 SDRAM components from various vendors