DesignWare minPower Components

 

Today's conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines. The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable DC Ultra™ to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications. Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption. In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable blocks that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.

By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic. The table below shows the overall improvements in area and power in datapath circuits as recorded from initial customers designing wireless connectivity and high-performance networking applications. While the total chip power reduction achieved with the DesignWare minPower Components will vary, initial customers have reported design power reductions ranging from 2 to 20 percent in tested modes.

DesignWare minPower Components

 

Highlights
Products
Downloads and Documentation
  • Innovative low power datapath architectures with lower switchings and glitches
  • Configured automatically by DC Ultra for most fitted implementation based on power costing and switch activities or transition probabilities
  • Smart architecture generation for lower leakage cell mapping
  • Integrated datapath gating within datapath blocks eliminates the timing overhead resulted from inserted isolation gates
  • Instantiated IP with enhanced clock gating and built-in isolation logic for better dynamic power
  • New data tracking IP reduce dynamic power consumption for pipelined architectures
  • Extend battery life for mobile applications by lowering the power consumption for circuits with extensive active times
  • Reduce power consumption for high-performance computing circuits
DW_fp_addsub_DGFloating-Point Adder/subtractor with Datapath Gating
DW_fp_add_DGFloating-Point Adder with Datapath Gating
DW_fp_cmp_DGFloating-Point Comparator with Datapath Gating
DW_fp_div_DGFloating-Point Divider with Datapath Gating
DW_fp_mac_DGFloating-Point Multiply-and-Add with Datapath Gating
DW_fp_mult_DGFloating-Point Multiply with Datapath Gating
DW_fp_recip_DGFloating-Point Reciprocal with Datapath Gating
DW_fp_sub_DGFloating-Point Subtractor with Datapath Gating
DW_fp_sum3_DG3-Input Floating-Point Adder with Datapath Gating
DW_lp_cntr_updn_dfminPower Low Power Counter with Dynamic Terminal Count Flag
DW_lp_cntr_up_dfminPower Low Power Up Counter with Dynamic Terminal Count Flag
DW_lp_fifoctl_1c_dfminPower Low Power Single clock FIFO Controller with Dynamic Flags
DW_lp_fifo_1c_dfLow Power Single Independent Clock FIFO
DW_lp_fp_multifuncminPower Low Power Floating-Point Multi-function Unit
DW_lp_fp_multifunc_DGminPower Low Power Floating-Point Multi-function Unit with Datapath Gating
DW_lp_multifuncminPower Low Power Multi-function Unit
DW_lp_multifunc_DGminPower Low Power Multi-function Unit with Datapath Gating
DW_lp_piped_divminPower Low Power Pipelined Divide
DW_lp_piped_eccminPower Low Power Pipelined Error Correction (ECC)
DW_lp_piped_fp_addminPower Low Power Pipelined Floating-Point Adder
DW_lp_piped_fp_divminPower Low Power Pipelined Floating-Point Divide
DW_lp_piped_fp_multminPower Low Power Pipelined Floating-Point Multiplier
DW_lp_piped_fp_recipminPower Low Power Pipelined Floating-Point Reciprocal
DW_lp_piped_fp_sum3minPower Low Power Pipelined 3-input Floating-Point Adder
DW_lp_piped_multminPower Low Power Pipelined Multiplier
DW_lp_piped_prod_summinPower Low Power Pipelined Sum of Products
DW_lp_piped_sqrtminPower Low Power Pipelined Square Root
DW_lp_pipe_mgrminPower Low Power Pipeline Manager

Description: 3-Input Floating-Point Adder with Datapath Gating
Name: DW_fp_sum3_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Adder with Datapath Gating
Name: DW_fp_add_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Adder/subtractor with Datapath Gating
Name: DW_fp_addsub_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Comparator with Datapath Gating
Name: DW_fp_cmp_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Divider with Datapath Gating
Name: DW_fp_div_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Multiply with Datapath Gating
Name: DW_fp_mult_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Multiply-and-Add with Datapath Gating
Name: DW_fp_mac_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Reciprocal with Datapath Gating
Name: DW_fp_recip_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Floating-Point Subtractor with Datapath Gating
Name: DW_fp_sub_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: Low Power Single Independent Clock FIFO
Name: DW_lp_fifo_1c_df
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Counter with Dynamic Terminal Count Flag
Name: DW_lp_cntr_updn_df
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Floating-Point Multi-function Unit
Name: DW_lp_fp_multifunc
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Floating-Point Multi-function Unit with Datapath Gating
Name: DW_lp_fp_multifunc_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Multi-function Unit
Name: DW_lp_multifunc
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Multi-function Unit with Datapath Gating
Name: DW_lp_multifunc_DG
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipeline Manager
Name: DW_lp_pipe_mgr
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined 3-input Floating-Point Adder
Name: DW_lp_piped_fp_sum3
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Divide
Name: DW_lp_piped_div
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Error Correction (ECC)
Name: DW_lp_piped_ecc
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Floating-Point Adder
Name: DW_lp_piped_fp_add
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Floating-Point Divide
Name: DW_lp_piped_fp_div
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Floating-Point Multiplier
Name: DW_lp_piped_fp_mult
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Floating-Point Reciprocal
Name: DW_lp_piped_fp_recip
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Multiplier
Name: DW_lp_piped_mult
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Square Root
Name: DW_lp_piped_sqrt
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Pipelined Sum of Products
Name: DW_lp_piped_prod_sum
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Single clock FIFO Controller with Dynamic Flags
Name: DW_lp_fifoctl_1c_df
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL
  
Description: minPower Low Power Up Counter with Dynamic Terminal Count Flag
Name: DW_lp_cntr_up_df
Version: DWBB_201612.4
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare minPower
Overview: DesignWare minPower Components
Documentation:
Examples: Direct Instantiation in Verilog
Direct Instantiation in VHDL