Synopsys 3DIO Platform

Synopsys 3DIO Platform is a specialized IO for multi-die integration. It offers versatile solutions for system-on-chip (SoC) designers to implement tunable, integrated multi-die design structures targeting HPC (AI), GPU, CPU, and mobile applications. The optimal area of the 3DIO Platform is carefully designed to be within the BUMP, providing significant advantages in implementation and signal routing.

Synopsys 3DIO Platform is architected to support 2.5D, 3D and SoIC package form factors, with flexible physical dimensions on u-BUMP or TSV integration. It comprises a portfolio of 3DIO products enabling various use cases: synthesizable 3DIO for automated placements of thousands of IOs on the bumps, synthesizable Source Synchronous 3DIO for building custom macros, and fully integrated 3DIO-PHY for high performance and fast time-to-market. Synopsys 3DIO Platform is part of the Synopsys IP offering for Multi-Die Solutions including UCIe (PHY, Controller, VIP) and HBM3 IP.

The Synopsys 3DIO Platform enables designers to create efficient chips in a faster time to market, accelerated with Synopsys 3DIC Compiler to ease integration and provide optimized power, performance, and area (PPA) for a given technology.

Read Article: Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)

Download Synopsys 3DIO Platform Datasheet



• Optimized for heterogeneous integration in 3D stacking

• Enabling designers the flexibility & scalability to accelerate multi-die integration   

• Flexible, scalable, and optimal PPA platform architected to support 2.5D and 3D packages

• Versatile offering tuned for various use scenarios, comprising:

  • Soft configurable 3DIO for flexible physical implementation
  • Synthesizable & scalable, source synchronous 3DIO for customized macros 
  • Fully integrated 3DIO PHY for optimal performance

• Compact integrated design, for smallest power & area (<50% of the hybrid bump pitch)

• Compatible with 3DIC Compiler, for fast timing closure