DesignWare Technical Bulletin Article

Search Tools


XGXS-PCS IP - PCS for 10G Ethernet eXtender Sublayer

Geetha R Arun

In June 2006 Synopsys added a new member to its Ethernet IP portfolio, the DWC Ether XGXS-PCS core, version 1.00a. This core, along with the Synopsys XAUI PHY IP, offers the XGMII-eXtender-Sublayer solution to the fast-growing 10Gigabit Ethernet market.


According to the IEEE802.3ae standard  that specifies the MAC and PHY protocol  for 10Gbps Ethernet, XGMII (10G Media Independent Interface) is the data interface between the 10Gbps MAC(Media Access Controller) reconciliation sub layer(RS) and the corresponding PHY layer devices. To facilitate longer physical separation on a circuit board while keeping the number of signal lines to a minimum, an optional layer is defined between the MAC and the PHY. This layer is called XGXS - XGMII eXTender Sub layer.  The extender layer comprises XGXS at the MAC/RS end and XGXS at the PHY end, with 10G Attachment Unit Interface - XAUI, in between them. The IEEE 802.3ae Clause 47 defines the specification for XGXS layer.

XGXS enables physical connectivity up-to 20" between the MAC and the PHY components across a circuit board, in a 10Gbps Ethernet system.

In addition to the extended connectivity, the 32 bit data bus (with 4 controls and clock in each direction) is reduced to self-clocked, 4 lanes of differential data at 3.125Gbps.

As mentioned earlier, the Synopsys solution for XGXS consists of 2 components:

  • XGXS-PCS - the digital IP that implements the PCS (Physical Coding Sub layer) function.
  • XAUI-PHY - the mixed signal IP, commonly known as SerDes or transceiver, which implements the PMA (Physical Media Access) functionality. It is also referred to as XGXS-PMA in the IEEE standard specifications.

XGXS- An overview

XGXS layer can be instantiated to directly interface to the XGMAC (referred to as DTE-XGXS) or next to the PHY (referred to as the PHY-XGXS). The diagram below shows where XGXS is instantiated in the context of a system environment.

Each XAUI-PHY module (x1 configuration) enables data transmission up to 3.125Gbps to the line-side. On transmit side, it provides serialization of the 10-bit wide encoded data presented by the PCS layer. On receive side, it recovers clock and data from the received data stream and sends 10-bit parallelized data, along with the clock to the PCS layer. For 10Gbps operation with XGXS-PCS, the Synopsys XAUI-PHY in x4 configuration is required.

The XGXS-PCS core is designed and developed to integrate seamlessly with the Synopsys XAUI-PHY. It interfaces with each of the 4 XAUI PHY transceivers via a 10-bit wide proprietary interface. It implements the standard Physical Coding Sub layer (PCS) functions like data encode/decode, idle control character conversion, data synchronization and lane-to-lane de-skewing and alignment.

Together, these 2 IPs, XGXS-PCS and XGXS-PHY(x4 configuration), offer the complete XGXS solution. This article outlines the features and functionalities XGXS-PCS digital IP core. Note that XGXS-PCS is also planned for integration with non-Synopsys XGXS-PMA transceivers in a future release.

XGXS-PCS  features and functional details

Data Interfaces

XGMII: XGXS-PCS interfaces to the XGMAC via a 32-bit wide data and 4 control lanes, clocked at 312.5 MHz in each direction. Alternatively, it can interface with the XGMAC using a 64-bit wide data interface (clocked at 156.25MHz) or 32-bit wide data interface (clocked at 156.5MHz), DDR.

XAUI-PHY (or XGXS-PMA) interface: This is a 40 bit wide interface (10bit/lane) single-ended and clocked at 312.5 MHz.

Transmit data path

This block gets the XGMII transmit data and transmit clock. The data path internally operates at 312.5MHz. Its main functions include:

  • XGMII (dual Data Rate or 64 bit Dual Data Width) data conversion to 32-bit SDR (Single data rate) at 312.5 MHz.
    When the XGMII data interface is configured for the IEEE802.3ae-standard 32-bit and DDR or 64-bit wide SDR, the data is converted to 32-bit wide bus operating at 312.5MHz.
  • Idle code conversion: The XG idle code characters are converted into randomized sequence of special codes. This is to enable data synchronization and lane alignment at the far-end receiver and reduce EMI amongst the lanes. This is done during IFG (Inter Frame Gap). 
  • 8b /10b encoding: In compliance with the 10GBase-X requirements, it implements PCS 8b to 10b data encoding. For each of the 4 the input data octet from XGMII and corresponding control character, it generates an equivalent 10-bit code group, in accordance with the IEEE 802.3 code mapping.

In addition, the transmit block also generates the test patterns for BERT(Bit Error Rate Testing).

Receive datapath

This block gets 4 groups of 10-bit raw data one from each of the XAUI-PHY core, along with the recovered clock. Its main functions are:

  • Data synchronization: The data synchronization logic receives unaligned data - 10bit/lane from each of the 4 XAUI lanes along with the recovered clock. Each lane is synchronized to the code-group-boundary based on the comma/K-code group detection. The synchronization is complete only when all 4 lanes are synced to the code-group boundaries.
  • 10b to 8b decoding: Each 10-bit code group is decoded to the corresponding octet.
  • Lane to lane deskew: The 4 lanes are de-skewed and the 4 octets of data are aligned to form a coherent 32-bit XGMII word. The de-skewing is performed by aligning the "A" code group. If lanes are not aligned within 5 clock cycles, it will result in an error condition.
  • Special character replacing the special code groups. That is, K, A, R characters are replaced with the idle characters.
  • Clock rate compensation: This is an optional function. If the application requires that the received data needs to be presented synchronous to the local clock, then idle characters are inserted or deleted to compensate for the "ppm" variations. The maximum variation supported is 200 ppm.  Always the minimum IFG of 64 bit times is maintained.
  • Data conversion to the XGMII interface: Depending on the selected XGMII interface, data is converted to 64-bit SDR or 32-bit DDR.

Control and Status Register (CSR) interface

XGXS-PCS implements 2 groups of register sets:

  • Standard register set: IEEE802.3ae Clause 45-specified registers. Based on the configuration in DTE or PHY mode, appropriate registers are included.
  • Vendor-specific register set: Registers specific to the Synopsys XGXS-PCS as well as XAUI-PHY control registers. Several controls to the XAUI-PHY core, like the analog loopback and other analog controls can be programmed in this register set.
  • The registers can be accessed using one of the 2 options:
  • MDC/MDIO interface: This is implemented as per the IEEE802.3ae clause-45. It is a serial interface, clocked at a maximum of 2.5MHz.  The application accesses the CSR using the management frame structure as defined in Clause 45.
  • MCI: This is a simple, generic microcontroller-like Interface. It is a parallel interface clocked at the same rate as the application clock frequency, used by the application to access CSR.

Test, diagnostics support

IEEE 802.3ae, Appendix 48-A compliant test patterns can be transmitted for BER (Bit Error Rate) testing. The patterns to be generated can be selected by programming the SR test register.

For diagnostics XGMII loopback is supported. XAUI PHY can also be programmed for loopback, by programming the XAUI PHY control register in the CSR set. XAUI-PHY control parameters can be controlled by writing into the registers. Conversely, the status information from the PHY like the PLL status etc. can be read out.

The errors detected at the PCS layer, like the invalid code groups, de-skew alignment error etc are counted and reported in the error counters.

Configurability through coreConsultant

The XGXS-PCS core is flexible and can be configured to suit the target application easily. This is done through coreConsultant. The configurable features are:

  • XGMII TX/RX data interface
    • 32-bit 315.MHz, SDR
    • 64-bit, 156.5MHz, SDR
    • 32-bit 156.5MHz DDR
  • Clock rate compensation feature in receive data path
  • Control and Status Register interface:
    • MDIO
    • MCI
  • DTE mode XGXS or PHY mode XGXS
  • OUI, Model number, revision number, etc.
  • Interface with the Synopsys XAUI-PHY or the non-Synopsys XGXS-PMA (supported in the next release)

Deliverables, packaging  and  licenses

The database is packaged as a Synopsys coreKit. It includes synthesizable RTL code. In addition, a verilog verification environment comprising of XGXS DUT( RTL for XGXS-PCS plus a behavior model of the Synopsys XAUI PHY transceiver) and Ethernet VIPs (XAUI and XGMII) is provided. In addition, a comprehensive verification suite consisting of directed test scenarios including test-suites used for UNH (University of New Hampshire) certification is provided.

Documentation consists of a databook, release notes as well as install guide and quick start document for ease of use.

Simulation scripts to support VCS,MTI,NC-Verilog, synthesis scripts for the Synopsys DC, Formal verification script for Formality as well as ATPG using Tetramax are packaged with the core.

CoreConsultant GUI also supports verification of RTL source and the gate level netlist. It also supports the physical design-flow including synthesis, Scan insertion and test pattern generation and formal verification.

The XGXS-PCS IP can be licensed for encrypted version of RTL using the license feature: DWC-XGXS-PCS.

For full access to the RTL code, the license required is: DWC-XGXS-PCS-SRC.


XGXS-PCS is released for general availability. After obtaining the required licenses, you can download via www.myDesignWare.com using your solvNet ID.