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New Release of DesignWare Verification IP for I2C is now available for download

The new release of DesignWare Verification IP (VIP) for I2C is now available for download. I2C is the latest DesignWare VIP to add support for the popular VMM methodology defined in the Verification Methodology Manual for SystemVerilog, enabling easy integration with constrained-random, coverage-driven environments. It also supports Verilog and VHDL testbenches. The I2C Verification IP supports all popular simulators and enables up to five times faster verification when used with the VCS comprehensive functional verification solution.

The DesignWare Verification IP for I2C provides an efficient and simple way to verify the I2C bi-directional two-wire bus. It provides support for standard, fast, and high speed operations. In addition, the I2C Verification IP has a rich set of configuration parameters to set clock synchronization and generation of the Serial Clock Line (SCL) to meet all clocking requirements. It can operate as a Master, Slave, or both and can change dynamically according to the stimulus applied. As a Master, the VIP can Start/Stop all possible transfers. As a Slave device it can detect Start/Stop conditions and perform data transfers according to the initiator request.

The following DesignWare Verification IP titles also support VMM testbenches in VCS and VCS-MX.

  • AMBA AHB 2.0, APB
  • PCI Express
  • OCP 2.0/2.1
  • Ethernet 10/100/1G/10G
  • USB 1.1, 2.0, OTG
  • Serial IO
  • Serial ATA

More Information on DesignWare Verification IP: http://www.synopsys.com/VIP