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What's New in 2006.06 DesignWare Library Datapath and Building Block IP

The DesignWare® Library introduced 21 new Building Block IP in the 2006.06 release. The DesignWare® Library Datapath and Building Block IP is tightly integrated Design Compiler (DC) and it is the part of DC installation. This release contains new Floating Point components, datapath functions, synchronizers, and new arbiters. All of these components are available in the DesignWare® Library at no additional cost.

This article provides a brief description and associated features of the new blocks.

Floating Point Components

The new DesignWare Floating Point components can be instantiated in both VHDL and Verilog. The precision of the floating point numbers is parameterized and covers all the IEEE formats.  The new Floating Point components can be synthesized with DC and are a superset of the Floating Point components based on Module Compiler technology. These components are useful in a variety of applications like graphics, signal processors and general purpose processors where floating point arithmetic operations, comparisons, and conversions are common.

These new Floating Point components take advantage of the DesignWare datapath generator technology that delivers better QoR than traditional technology.  The DesignWare datapath generator is tightly integrated in DC and supported by the Galaxy Design Platform.  When generating the datapath circuits, the datapath generator takes into consideration the full timing context of surrounding design and the characteristics of technology library to generate hybrid datapath structures best fitted for the design target.  The new Floating Point components not only save user development effort but also deliver better QoR than many other alternatives, such as 3rd party IP.

Verification of Floating Point library is not trivial because of the complexity of the components. These components have modules for alignment, normalization, and rounding apart from regular arithmetic operation.  The DesignWare Floating Point components are extensively verified by making use of IEEE reference model, simulating the test vectors generated by different CPUs, testing the special cases like overflow, underflow and normal/denormal boundary and random tests. Because these components are tightly integrated with Galaxy Design Platform, they can be verified by Formality and are fully compatible with DFT Compiler and Power Compiler.

The DesignWare Floating Point components are designed with the flexibility to meet a wide range of application requirements.  They can be parameterized to support different sizes, precisions (half, single, double, or custom) and cost requirements.  For example, customers can trade off IEEE compatibility by setting the parameter ieee_compliance to “0” for better area.

In addition to traditional floating point operation support, the DesignWare Floating Point components include the support for multiple operands that are popular in certain applications, such as graphics.  The multiple operand component sum3 gives the result equivalent to [(a+b)+c], and it is faster than using two adders for the same operation. The other multiple operand component is sum4, which gives equivalent result [ ((a+b)+c)+d].

The following are the features of the Floating Point components:

  • The precision of the floating point numbers is parameterizable. The parameters cover all the IEEE formats.
  • The parameter range for exponents is from 3 to 31 bits.
  • The parameter range for the significand or the fractional part of the floating point number is from 2 bits to 253 bits.
  • Complete IEEE 754 compliant and can be controlled with the ieee_compliance (=FALSE by default) parameter.
  • Functionally backward compatible with Module Compiler based components.

The following is the list of new Floating Point components:

DW_fp_addsub Floating Point Adder/Subtractor
DW_fp_add Floating Point Adder
DW_fp_sub Floating Point Subtractor
DW_fp_cmp Floating Point Comparator
DW_fp_div Floating Point Divider
DW_fp_flt2i Floating Point to Integer Converter
DW_fp_i2flt Integer to Floating Point Converter
DW_fp_mult Floating Point Multiplier
DW_fp_sum3 3-input Floating Point Adder
DW_fp_sum4 4-input Floating Point Adder

For detailed information about DesignWare floating point components, refer to the following:

Datapath Functions

The datapath functions are collection of HDL functions that can be called in a design’s RTL code. These functions describe dedicated datapath functionality (for example, a blend function which is used in graphics) in synthesizable RTL code. These datapath functions are made available through packages in VHDL and through include files in Verilog.

The following are the features of DesignWare datapath functions:

  • Ease of use: Simple functional call
    assign z = DWF_dp_absval (a * b) + c
  • Functional Correctness: These functions are pre-verified
  • Best Quality of Results (QoR): Since the code is optimized for datapath synthesis with Design Compiler.
  • Design and Flow integration: datapath function’s HDL code tightly integrates into surrounding datapath functionality, allowing high-level optimizations and datapath synthesis. Also, they are tightly integrated in to Design Compiler datapath synthesis flow.

The following is the list of DesignWare datapath functions:

DWF_dp_absval Absolute Value
Graphics Alpha Blend
Arithmetic Saturation
DWF_dp_sign_select Sign Selection / Conditional Two’s Complement

For detailed information about DesignWare datapath functions, refer to the following:

Synchronizer Family

The Clock Domain Crossing (CDC) IP is used to safely connect signals between two different clock domains. Each synchronizer block uses a wide variety of clock domain crossing schemes.  Detecting the clock domain crossing issues is difficult in RTL simulations, since these issues are real-world phenomenon and difficult to predict. DesignWare synchronizers are carefully verified and validated in real designs. These synchronizers can be used in many applications like, data bus controllers or any interface sending parallel data between two clock domains.

Some of the features of the synchronizers are as follows:

  • Parameterized data bus
  • Parameterized synchronizing stages
  • Parameterized test feature
  • Parameterized output registration/all outputs registered
  • Ability to model missampling of data on source clock domain

The following is the list of synchronizers:

DW_data_sync Data Bus Synchronizer with Acknowledge

Data Bus Synchronizer without Acknowledge

DW_gray_sync Gray Coded Synchronizer

Pulse Synchronizer with Acknowledge

DW_stream_sync Data Stream Synchronizer

For detailed information about DesignWare synchronizer components, refer to the following:


The previous arbiter components (DW_arbiter_2t, DW_arbiter_dp, DW_arbiter_fcfs, and DW_arbiter_sp) are replaced by the following new components:

DW_arb_2t Two-Tier Arbiter with Dynamic/Fair-Among-Equal Scheme
DW_arb_dp Arbiter with Dynamic Priority Scheme
DW_arb_fcfs Arbiter with First-Come-First-Served Priority Scheme
DW_arb_sp Arbiter with Static Priority Scheme

With different arbitration priority schemes and features like park, lock, and parameterized number of clients, these arbiters are suitable for control applications, networking, and bus interfaces.

The input signals added to the newer arbiter components are:


Synchronous reset for all registers (active low)

enable Enables clocking (active high)

For detailed information, refer to the following:

Arithmetic and Combinational

The additional Building Block IP components added are the DW_piped_mac and DW_lsd.


Pipelined Multiplier carry-save Accumulator (MAC). This is an essential part of arithmetic intensive applications like DSP.

The following are the features of DW_piped_mac:

  • Integrated multiply and carry-save accumulate
  • Built-in pipeline power management
  • Parameterized pipeline stages, operand and output widths
  • Launch identifier tracking propagation

For more information, refer to the datasheet:


Leading Signs Detector. Contains two outputs, dec and enc and an input “a”. The dec output is a decoded one-hot value of the “a” input vector with a “1” at the least significant (right-most) sign bit position of “a”. The output enc represents the number of extended sign bits found (from the most significant bit) before the least significant sign bit of input “a”.

For more information, refer to the datasheet:

Where to find 2006.06 DWBB IP

All of these new 2006.06 DWBB IP components are bundled with 2006.06 Design Compiler. If you are using an older version of Design Compiler (2005.09, for example), you can download and then perform an overlay installation of the 2006.06 version of DesignWare Building Block IP:
Designware Building Block Download