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Testing PCI Express 5.0 PHY Receiver Performance in the Absence of a Controller

During the initial PCI Express® (PCIe®) PHY development stages, testing the electrical characteristics can be difficult. Conducting tests such as jitter tolerance with automated test suites becomes very challenging since most automated test suites rely on a negotiated linkup with the device under test (DUT). This requires validating the integration of the system before starting the PHY electrical performance evaluation. An alternative method to getting expedited electrical results on the PHY is to test the receiver in the absence of the media access controller (MAC).

This white paper describes a methodology for jitter tolerance testing without using the controller to negotiate a link. To perform a receiver jitter tolerance test, engineers need to calibrate the stressed eye signal to accurately test the receiver performance. Each small component in the jitter tolerance test plays an important role in the final result. In addition, the paper outlines a procedure for calibrating the stressed eye representing the worst-case loss characteristics, and shows the jitter tolerance testing of the Synopsys PHY by using the Pattern Matching capability.

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