Testing Embedded MRAM IP for SoCs
The challenges of embedded memory test and repair are well known, including maximizing
fault coverage to prevent test escapes and using spare elements to maximize manufacturing
yield. With the surge in availability of promising non-volatile memory architectures to augment
and potentially replace traditional volatile memories, a new set of SoC level memory test and
repair challenges are emerging. With momentum building for Spin Transfer Torque MRAM
(STT-MRAM) as the leading flavor of embedded MRAM technology, this white paper focuses on
unique test challenges for STT-MRAM on-chip memory while considering needs for automotive
applications. To select an appropriate memory test and repair solution for embedded MRAM,
designers need to consider factors such as the special needs of performing trimming during
production test, augmented memory fault detection algorithms specific to MRAM architectures,
and maximizing manufacturing yield of the process sensitive MTJ (Magnetic Tunnel
Junction) bit cell.
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