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From Design to Test: Developing High-Reliability MTP NVM

Developing high-quality NVM IP requires going beyond just design techniques and architecture and involves a significant investment in silicon testing to demonstrate the quality and reliability performance.

As the use of embedded NVM, and particularly embedded MTP NVM, expands into applications and products that have not historically used NVM, design engineers must familiarize themselves with the appropriate design and testing methodologies to select a supplier who not only develops reliable NVM, but who demonstrates the performance in silicon.

Failing to select an MTP NVM IP that has the reliability level appropriate for the end application can result in production yield loss or field failures, both of which can have a significant impact on the end product’s profitability and manufacturability. An added benefit of choosing an MTP NVM IP supplier with the knowledge and the methodology to demonstrate the required reliability is that in many cases data from the IP supplier can be used to augment the end product’s qualification and reliability data, thereby saving both cost and effort in the development and release of a new SoC product.

Developing and demonstrating high-reliability MTP NVM requires experience and knowledge as well as silicon testing capabilities. Synopsys is uniquely positioned in the MTP NVM IP space by having not only the technical expertise in MTP NVM design and test, but also the facilities and capabilities to implement the best-in-class processes and procedures.

The Synopsys DesignWare® AEON® family of NVM IP has been designed to deliver detailed, silicon based performance data on endurance, retention and write disturb. Each DesignWare AEON IP product is architected to optimize performance for particular applications, whether it is real-time data logging, high precision trimming, ultra-low power wireless or customer personality settings.

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