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Scaling ADC Architectures for Mobile and Multimedia SoCs at 28-nm and Beyond

Modern systems-on-chips (SoCs) are typically implemented in the most advanced process nodes available to take advantage of the smaller and faster properties of that process. This trend has allowed SoC architects to effectively address end users’ expectations that each new product generation will offer higher functionality and performance, lower power and, hopefully, lower cost.

According to Moore’s Law, SoC density is expected to increase by 1.5X-2X in every new process generation, and power consumption must reduce by the same factor. This scaling comes naturally in digital circuits that basically consist of interconnected switches. For analog circuits to achieve similar scaling factors, they must employ the higher speed and processing power available by Moore's Law scaling. For example, more compact analog blocks can perform the same functions of more complex ones by relying on digital compensation, calibration, and higher processing speed, leading to the concept of digitally enabled analog circuits.

This white paper elaborates on how analog to digital converters (ADCs) can work with Moore’s Law to move with the power and area scaling trends that are common for digital circuits. It will:

  • Compare the main ADC architectures and conclude that the Successive-Approximation Register (SAR)-based ADC is very well positioned as the architecture of choice for medium- and high-speed 28-nm ADCs.
  • Describe implementations of the SAR ADC architecture that reduce power consumption and area use, enabling SoC designers to successfully integrate these analog components in their next SoCs.
  • Present the DesignWare SAR-based ADCs for 28-nm and explain how they benefit from the characteristics of the advanced process nodes to yield analog IP that adheres to the area and power scaling paradigms of the digital circuitry, with improved overall analog performance.

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