By Richard Solomon, Sr. Technical Marketing Manager, PCI Express Controller IP
While PCI Express® has become the dominant I/O interconnect in PCs from ultrabooks to enterprise servers, it has largely failed to break into the tablet and smartphone space due to these applications' ultra-low power requirements. Great strides have been made in reducing PCI Express power with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, and new power-saving L1 sub-states. However, the challenges of driving PCIe’s high data rates across 16”-20” server channels have kept the power requirements of PCIe® PHYs well above what mobile devices can tolerate. For PCI Express to extend into the ultra-low power world of mobile devices, something drastic would have to be done.
Back in 2012, Synopsys and other companies founded a new PCI-SIG Working Group whose aim was to reduce PCIe power and bring its protocol, programming models, and wide spectrum of designs to the mobile space. Ultimately the group decided to replace the “legacy” PCI Express PHY and specify the MIPI Alliance’s M-PHY due to its proven power efficiency and range of speeds. In September 2012, the PCI-SIG and MIPI Alliance announced their collaboration with the ultimate goal of allowing device designers to easily move existing PCI Express designs to the new specification with little or no change to their existing PCI Express software infrastructure. Work proceeded quickly and by early 2013 the two groups announced the first version of the
M-PCIe™ Engineering Change Notification (ECN).
The M-PCIe ECN provides dramatic power savings over similar PCIe designs. Note that because M-PCIe is an ECN against the PCI Express 3.0 Base Specification, both documents are needed to completely specify an M-PCIe device. Figure 1 shows how implementing the M-PCIe ECN impacts a typical PCIe Root-Complex to Endpoint device path. A standard PCI Express path is represented on the left, and the new M-PCIe connections are shown on the right. The upper PCIe protocol layers– the Transaction Layer (TL) and Data Link Layer (DLL) – are unchanged in the M-PCIe devices. This ensures that the PCIe programming models are unchanged, and the application logic in each device can remain almost unchanged. The PCIe PHYs are replaced by M-PHYs, and the PHY interface changes from PIPE to RMMI. Only the Logical PHY Layer (LPL) is unique new logic for M-PCIe implementations.