When multiple CPUs share a common memory space, they gain performance from communicating the cached and/or cacheable state of pieces of that memory. In this way, each CPU can safely work on a portion of a common data set without having to use (slow) software semaphores to control access. If CPU A has a piece of memory cached, it can ensure that CPU B does not modify that same memory space or use a stale copy of the data. CCIX extends this communication so agents other than CPUs can participate, which enables hardware accelerators to gain the same benefits. CCIX’s coherence protocol is also vendor-independent, so CPUs, GPUs, and other accelerators can all participate equally and without onerous licensing restrictions.
To better understand cache coherency, let’s examine a coherence protocol in common use for some time now known as MESI. The acronym MESI refers to the four possible states of each cache line in the system: Modified, Exclusive, Shared, or Invalid. Modified means a cache line is stored ONLY in the current cache, and is different from the data in main memory (“dirty” in cache parlance). Any other agent attempting to read from an address marked somewhere in the system as Modified will cause the cache (which has the modified data for the address) to write the data back to main memory before the read may proceed. An Exclusive cache line is also stored ONLY in the current cache, but it matches the data in main memory (“clean” in cache parlance). If the agent owning that cache line makes changes to it, the state will switch to Exclusive. A Shared cache line is also “clean” like an Exclusive one, but it may ALSO exist in other cache(s) in the system (where it would also be in the Shared state). Finally, an Invalid cache line is exactly what it sounds like – an unused or no longer valid cache line. Clearly the various caches in such a system must communicate several pieces of information with each other. They must support snooping or monitoring of bus transactions from other agents to determine when their cache state needs to change, and they must have some means of communicating state changes to other caches in the system.
The CCIX protocol specification defines a set of cache states and associated messages and mechanisms to accomplish this same general type of behavior. While full details are available only to CCIX Consortium members, this article will give a high-level overview of the protocol specification.