DesignWare Technical Bulletin
In-depth technical articles, white papers, videos, webinars, product announcements and more
See how combining an ISP’s correction technique with a vision processor’s machine learning provides higher quality results.
Address the demands of CI and HCI systems with IP that is optimized for processing, memory and connectivity.
Learn how Percepio’s Tracealyzer for OpenVX visualization tools enable designers using ARC EV6x processors to optimize their applications for maximum performance.
Learn about the design challenges of moving to a PCIe 5.0 based interface and how proven, optimized IP can help.
Meet power, performance, and area targets for artificial intelligence SoCs by integrating flexible building blocks of logic and memory.
Learn how to choose the DDR SDRAM or HBM memory interfaces to best meet your AI, automotive, or mobile application requirements.
Ethernet Time-Sensitive Networking Applications Beyond Automotive
Efficient Low-Cost Implementation of NB-IoT for Smart Applications
Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
Digital Signal Processing for Frequency-Modulated Continuous Wave RADARs
Safety and Security from the Inside - a SoC's Perspective
Enabling Concurrent Wireless Connectivity with DesignWare IP
Inuitive Demonstrates NU4000 Artificial Intelligence SoC with DesignWare EV6x at CES 2019
Accelerating Development of DesignWare Mixed-Signal PHY IP with Custom Compiler
Making Sense Of DRAM
PAM-4 56G Ethernet PHY IP Performance Exceeding Specification Limits
CCIX SC18: Synopsys’ DesignWare CCIX Controller and PHY IP Solutions
StradVision Deep Learning Demo for Autonomous Driving at ARC Summit 2018
SecureRF Accelerates Cryptographic Processing with DesignWare APEX Extensions
MulticoreWare Demonstrates Object Tracking and Pose Recognition at ARC Summit 2018
Building AI SoCs