Synopsys Processor Solutions Seminar - SoCal

Processor Solutions for Automotive, Industrial, and Consumer Edge Applications

Synopsys held onsite seminars in its Irvine and San Diego offices, where  experts discussed the latest technologies and trends in embedded processor and security IP. If you are interest in the topics that were presented, contact us!

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As embedded systems become more complex and integrate greater functionality, designers are faced with the challenge of developing more powerful but more energy-efficient SoCs and subsystems. For the processors that power these applications, efficiency is paramount. Synopsys’ DesignWare ARC Processors are optimized to deliver the maximum performance for any given power or area budget. For designers who are looking to design a custom processor, the ASIP Design tool automates the design of application-specific processors. Whether you need configurability or a fully customized processor, Synopsys’ Processor Solutions portfolio can meet your requirements.

Join us at one of these free seminars to learn how Synopsys' processor and security solutions can help you achieve your design goals in a variety of vertical markets including automotive, industrial, and consumer products for applications at the edge or in the cloud. Lunch will be served. 

Agenda

Time

Description

10:00 – 10:10

Check-in

10:10 – 10:20

Welcome & Opening Remarks

10:20 – 11:10

Harnessing the Data Explosion Generated from Artificial Intelligence
Ron Lowman, DesignWare IP AI Strategic Marketing Manager,
Synopsys

Autonomous vehicles, augmented reality, machine vision, the internet and augmented reality are all increasing rapidly in capability. The common link in these capabilities is the large amounts of data that they generate. Most of the data is being created outside of the data center and transporting data from where it resides to the core or cloud for processing is becoming challenging. As data grows Artificial Intelligence will be used to manage it focusing on where data is stored, when it is moved and where it is processed. Offline processing will also increase, and AI can be used to process the data and then move it later to the cloud as needed. This presentation will look at the challenges that we face with data and how we can enable you to address them.

11:10 - 12:00

Designing Embedded Security using Hardware Secure Modules (HSMs) w/ Root of Trust
Andrew Elias, Senior Security Architect, Synopsys

The DesignWare tRoot Hardware Secure Modules (HSMs) offer silicon-proven, self-contained security solutions with Root of Trust for a wide range of applications, including IoT, industrial control, networking, media and mobile devices. The DesignWare tRoot HSMs with Root of Trust provide designers with a Trusted Execution Environment (TEE) that protects sensitive information and data processing within their system-on-chips (SoCs) and communication with external entities.

12:00 - 1:00

Lunch

1:00- 1:50

Designing Application Specific Processors for AI Acceleration
David Florez, Sr. Corporate Applications Engineer, Synopsys

Deep learning is making its way into various application domains. The embedded vision market has embraced deep learning algorithms based on convolutional neural networks (CNN). Algorithms capturing dynamic temporal behavior in the form of recurrent neural networks (RNN) are being applied for sound processing and language translation systems. In such a dynamic environment, traditional SoC architectures with a microprocessor and hardwired accelerators no longer suffice. We will illustrate by example how ASIPs reconcile the needs for performance and flexibility. We will present ASIP architectures for two deep learning functions: (i) the acceleration of activation functions in LSTM networks, and (ii) simultaneous localization and mapping (SLAM).

1:50 - 2:40

Balancing Performance and Efficiency by Right-Sized Processor Selection in DSP Systems
Graham Wilson, Product Marketing Manager, ARC DSP Processors, Synopsys

Automotive applications such as Advanced Driving Assist Systems (ADAS), engine management, and powertrain require increasing levels of complexity as well as high levels of precision and accuracy in terms of algorithms and data formats. As algorithm complexity grows, system architects are developing their algorithms with tools such as MATLAB, which work in high-precision data formats such as half and single precision floating point.

These large amounts of computation need a specific core for large vector floating point DSP. The ARC VPX5 processor has three dedicated vector floating point computation pipes that gives industry-leading levels of throughput, as well as hardware acceleration for linear algebra mathematical functions. An overview of the VPX5 DSP processor will be given, as well as the complete ARC DSP Processor portfolio.

2:40 - 3:00

Break

3:00 - 3:50

Designing SoCs for Automotive ADAS Systems at ASIL D Functional Safety Standards
Ron DiGiuseppe, Automotive IP Segment Manager, Synopsys

Drivers are the biggest uncertainty factor in cars, and advanced driver assistance systems (ADAS) are helping to mitigate human error and make the roads safer. Designing SoCs for ADAS applications, including lane departure warning, adaptive cruise control, and autonomous vehicles that can ‘see’ in fog, heavy rain, pitch darkness, and air pollution, requires ASIL Ready processor IP. In this presentation, we will describe how to use functional safety processor IP to design safe SoCs that can meet the highest safety levels, up to ASIL D, for high-performance in-vehicle processing.

3:50 - 4:40

Applying New Vision and Deep Learning Trends to Edge Applications
Rick Furtner, Sr. Field Applications Engineer, Synopsys

Embedding computer vision and deep learning at the edge remains challenging today because of the huge computational and memory requirements and due to the pace of innovation of algorithms for modern vision and sensing tasks. CNN graphs particularly are rapidly evolving to improve the accuracy and speed of learning and inference. Mapping these vision and deep learning algorithms on low power embedded platforms are demanding on computational complexity, bandwidth and accuracy. In this presentation, we will discuss the latest computer vision trends and deep learning techniques for embedded platforms and how these trends are shaping the latest enhancements to the DesignWare EV Embedded Vision Processor IP family.

4:40 - 5:00

Wrap up