To promote rapid adoption of SSIC, the USB-IF aligned SSIC with the MIPI Alliance’s gigabit-speed, on-PCB, chip-to-chip PHY called the MIPI M-PHY. The M-PHY standard consumes lower power and offers greater flexibility than USB 3.0 PHYs. M-PHYs can come in three speeds called Gears. Gear1 operates at 1.25 or 1.45 Gbps, Gear2 at 2.5 to 2.9 Gbps, and Gear3 up to 5.8 Gbps. In addition, M-PHYs can have 1, 2, or 4 lanes. Each lane has x pins, so 2 lanes have 2x pins and 4 lanes have 4x pins. These lane configurations offer flexibility either to run in multiple parallel lanes at slower clock speeds to save power, or to run at faster speeds but consume fewer pins. Since many SoCs are pin and/or pad limited, designers often choose the faster Gear3 standard to save pins. A MIPI 1 lane PHY has 16 pins. A standard USB 3.0 PHY has at least 15 pins including USB 2.0 D+ and D-; USB 3.0 Tx+,Tx- Rx+, Rx-, power, and ground pins.
The MIPI Alliance and USB-IF worked together to standardize the interface between USB 3.0 controllers and MIPI M-PHYs. According to the standard, the USB 3.0 controller uses a standard PIPE interface, which is the same interface for the USB 3.0 path to a USB 3.0 PHY. While the PIPE interface is preserved, the system still needs an interface to a standard M-PHY. The M-PHY v2.0 specification defines the SSIC interface to the M-PHY as the Reference M-PHY Module Interface (RMMI). The logic bridge between the USB 3.0 controller and the M-PHY is called the PHY Adapter. While it sounds simple, the PHY Adaptor is complex as it must synthesize and operate with the controller and the PHY. It must support USB 3.0 power savings modes (U1, U2, U3, and U4) while supporting 1, 2, or 4 lanes and/or Gear1, 2, or 3 speeds.