DesignWare Hybrid IP Prototyping Kits for Prototyping, Software Development & Integration in 64-Bit ARM Processor-Based Designs

Introduction

Software stacks for ARM® based processors are getting more and more complex. Full vertical software integration of hardware IP requires significant work in many software layers. Starting with bare metal drivers in the secure boot firmware, drivers need to be developed and optimized. This also needs to be done for the second stage boot loader (UEFI) and of course for the main operating system such as Linux. End-to-end testing can only be performed when taking the higher level application software stack into account, such as Android.

All those objectives place challenging demands on the software development targets used by software teams. Excellent debugging and tracing capabilities are needed across all software layers deep into the hardware to make the debugging productive. This article introduces a new hybrid prototyping kit for accelerating DesignWare® interface IP driver development and integration into a 64-bit ARM processor-based system with a Linux software stack. The underlying technology of the DesignWare Hybrid IP Prototyping Kits combines the benefits of virtual and physical prototyping.

DesignWare Hybrid IP Prototyping Kits

DesignWare Hybrid IP Prototyping Kits bundle all necessary software and hardware components that are needed to start development out-of-the-box. The kits pre-integrate a Virtualizer™ Development Kit (VDK) and an FPGA-based DesignWare IP Prototyping Kit. The Hybrid IP Prototyping Kit includes proven DesignWare IP reference designs with Linaro Linux software stack and drivers on a HAPS-DX prototyping system with an analog PHY daughter board as shown in Figure 1. This setup serves the following major software development needs:

• First, the VDK, a software development kit using a virtual prototype as the development target, enables DesignWare IP software development on the latest ARM Cortex processors long before the processor’s RTL becomes available. Therefore, the virtual prototype embeds an ARM-supplied simulation model of the processor.
• Secondly, the FPGA-based DesignWare IP Prototyping Kit allows software developers to test scenarios where real-world interactions and special interoperability conditions are critical.
• Third, the whole system can be debugged by bringing up a standard third-party software debugger such as Lauterbach TRACE32®, ARM DS-5™ or GNU GDB.
• Fourth, deep trace debug features extend the debug scope to critical hardware aspects such as interrupt lines.

And lastly, the entire setup is pre-verified and includes a complete pre-built ARMv8 Linaro Linux software stack along with Synopsys reference device drivers for the specific DesignWare IP.

The VDK is binary software compatible with the ARM Base Platform specification and therefore is referred to as the reference VDK for ARMv8 Base. This specification is used by ARM and the Linaro organization for bringing-up and evolving open source software for the latest ARM processors. The specification covers the components, the platform memory-map and interrupts. The VDK within the DesignWare Hybrid IP Prototyping Kit hosts a model of an ARMv8 big.LITTLE™ subsystem with four Cortex®-A53 processors and four Cortex-A57 processors, cache coherent interconnect and ARM’s generic interrupt controller. Furthermore, various other peripherals like I/O devices such as keyboard and mouse interfaces, a color LCD controller, an Ethernet controller and several UARTs are included. The peripheral simulation models are equipped with virtual I/O capabilities so that the user can access the real Ethernet network from its software stack. Similar to a physical development board, the VDK enables the development of a wide range of software types. Those range from Unified Extensible Firmware Interface (UEFI) and Linux driver development to the hardware adaptation layer for DesignWare IP in context of Android. The performance of the VDK is sufficient to boot Linux in less than a minute or perform an Android 5 (Lollipop) warm-boot in approximately ten minutes.

A unique capability of the reference VDK for ARMv8 Base is its extensibility through a well-defined extension interface. This interface is used to complement the Base specification with custom extensions such as VDK simulation models of custom peripheral subsystems developed with the Synopsys Virtualizer tool suite. The interface is oriented at ARM’s LogicTile Express interface which again ensures software compatibility with standard drivers for the LogicTile Express infrastructure such as the configuration controller. The DesignWare Hybrid IP Prototyping Kit re-uses the same interface for coupling the VDK with the HAPS-DX7 system.

The IP Prototyping Kit within the DesignWare Hybrid IP Prototyping Kits is preloaded and pre-validated with a specific RTL reference configuration of the target DesignWare IP and all supplementary IP, such as transactors, which are essential to interface with the VDK. The transactors for ARM AMBA® interconnect connect the IP Prototyping Kit and VDK together -- AXI3 transactors (one primary and one secondary) and a GPIO transactor for interrupts are in place.

Probes have been added to increase the debug and trace visibility for this interface. DesignWare IP licensees will be also able to modify the DesignWare Hybrid IP Prototyping Kits using a fast iteration flow. Additionally, the user is able to tailor the instrumentation for tracing and debugging using the ProtoCompiler DX tool to make visible internal hardware signals of the prototype design.

For highest performance, all components of the DesignWare Hybrid IP Prototyping Kits, the link and transactors, need to be optimized for speed. Therefore, the DesignWare IP Prototyping Kit is connected to the VDK host machine using Synopsys’ high-bandwidth UMRBus (Universal Multi-Resource Bus) over a PCIe interface reaching typical transfer speeds of 400+ Mbps.

For example, playing back a 30 second SD H.264 video as shown in Figure 2, which is streamed from a USB pen drive plugged into the PHY daughter board, mounted using the VDK’s DesignWare USB xHCI driver, and decoded using the ffmpeg application, takes approximately 2 minutes using a recent laptop host.

The setup of the DesignWare Hybrid IP Prototyping Kit is as easy as connecting the prototypes using a PCIe cable to the host PC through a provided PCI-4_MGB kit, and mounting the PHY daughter board on the sockets of the HAPS-DX7. After the installation of the VDK software on the host PC, the system is ready to use and the example Linux can be booted.

Software Debugging

The DesignWare Hybrid IP Prototyping Kit comes with pre-built images of ARM’s trusted firmware, UEFI, Linux and an open embedded file system containing Linux tools and libraries. Furthermore, an entire download and build framework for the above software components is included. This allows software developers to immediately edit and rebuild the Linux software stack without having to search numerous community web pages with complex readme, download and installation steps. Also, the device tree kernel configuration file is automatically generated and any ARMv8 kernel can be exercised without going through manual porting steps.

Debugging can be performed instantly with industry-leading debug tools. One or more embedded software debuggers can be individually connected to one of the eight processors in the system, or a debugger can be connected to all processors in symmetric-multi-processing debug mode.

Debugging is performed in “stop” mode. If the target is suspended by one debugger, the entire target will be suspended. During this time, all virtual components (i.e., the ones which form the VDK portion) of the target halt their state. No timers expire, no watchdog peripherals time out, no interrupts are generated which corroborate the system state, etc. This synchronicity does not apply to all aspects for the physical part of the prototype. During suspension of the target, the clocks of the HAPS-DX and daughter board continue to tick. Since driver debugging is a key use case for the DesignWare Hybrid IP Prototyping Kit, we have paid special attention to the fact that the target remains stable during debug scenarios. During the suspension of the VDK, debug accesses to the design on the HAPS-DX can be performed. Figure 3 shows the debugging of the USB 3.0 Host interrupt handler during playback of a video from a USB stick plugged into the slot on the PHY daughterboard.

System Debugging

A majority of problems and bugs which appear during bring-up and testing of drivers require debugging beyond a single software thread. Tracing a defect behavior from the user-level symptom to the root cause inside a software function requires understanding of the interaction of the various hardware and software entities. Those can be user-level software processes such as test benches or applications, middleware libraries, Linux kernel drivers, firmware functions and the underlying (IP) hardware. The synchronization and communication mechanisms between hardware and software are very versatile. Before a hardware interrupt can arrive at the user-level process, a sensitive chain of events has to be processed. This involves an interrupt rippling through multiple ARMv8 exception levels, the driver communicating with the peripheral through peripheral I/O, potentially triggering MMU exceptions for virtualized peripherals and interacting with the kernel scheduler to wake up the user process.

Software developers using DesignWare Hybrid IP Prototyping Kit have the ability to extend the debug scope from thread-level software debugging to system-level hardware and software interaction debugging using the VP Explorer tool as shown in Figure 4. VP Explorer can probe the software and (IP) hardware status for interactive debugging and tracing, and can present hardware and software events together for more productive hardware/software debugging. VP Explorer provides deep visibility into the processors and peripherals on virtual side. Moreover, VP Explorer offers visibility into important aspects of the IP design on the FPGA-based IP Prototyping Kit.

A key challenge for any type of integration debugging is to not get lost in details and first understand the problem from a system perspective. VP Explorer enables designers to explore a top-down root cause analysis by abstracting the system execution. Its Linux-aware tracing allows software developers to follow through the various user- and kernel-level threads and interrupt handlers along with the Linux kernel’s debug and verbose messages.

As an example, on a Linux kernel panic message, the user can select the message, identify the process and zoom into the details to understand the exact location in the software which may have triggered a termination exception by writing to an unmapped address. From a hardware perspective, the user can put a watchpoint on the interrupt line of the HAPS-DX7 interface within the IP Prototyping Kit, a watchpoint on the processor’s IRQ exceptions and follow through the processor handling the interrupt in the firmware and kernel driver. The ability to get a bird’s eye view on the system at once than rather debugging components individually is essential for integration debugging. VP Explorer offers the user the possibility of increasing the level of tracing detail from software processes down to signals, registers and bus transactions.

The memory mapped peripheral registers of the design on the HAPS-DX7 can be inspected directly from VP Explorer. In case deeper visibility into the hardware is required, the user can take advantage of the HAPS Deep Trace Debug (DTD) capabilities. DTD is a sample based high capacity storage using internal FPGA memory or expanded on-board DDR3 memory with up to 8 GB for debugging purposes which can be configured using HAPS ProtoCompiler-DX. By default, the Hybrid IP Prototyping Kit is pre-built and instrumented with a set of relevant internal signals for tracing and observability with respect to the DesignWare IP. As required for the development, the set of tracing signals can be updated with HAPS ProtoCompiler-DX RTL instrumentor. It provides high flexibility to instrument additional signals by simply modifying a single file. This file will be used as input during the ProtoCompiler-DX compile run and for creating a new build to be used in HAPS-DX FPGA system. Once a trigger condition has occurred, all the previous instrumented signals will immediately start recording and will be stored into the selected memory location which can later be extracted and analyzed in a standard RTL waveform viewers (e.g. Verdi, GTKWave, Discovery Visual Environment (DVE)).

HAPS ProtoCompiler-DX RTL Instrumentor (Figure 5) allows users either to work through a command line mode or in a GUI mode for a more intuitive navigation through the menus for settings and configuration. Both modes provide the same output and result.

Conclusion

A DesignWare Hybrid IP Prototyping Kit provides all essential hardware and software components to enable DesignWare IP software development. A DesignWare Hybrid IP Prototyping Kit is an extensively tested and fully proven, out-of-the-box solution for software development for a specific DesignWare IP title. It provides an instantly productive software development platform for DesignWare IP to accelerate the integration of the IP into an ARM-based software stack. The Hybrid IP Prototyping Kit comes with all the reference designs, drivers, tools and script files required to quickly modify the reference IP configuration and rebuild it onto the prototyping kit using the proper DesignWare IP licenses. Furthermore, a complete build environment for all parts of the Linaro Linux software stack are bundled with the kit to instantly rebuild the software with user-customized DesignWare IP drivers. A DesignWare Hybrid IP Prototyping Kit fits seamlessly into existing software development flows as it supports all major third-party software debug tools for ARM Cortex processors. The Virtualizer VDK’s VP Explorer and HAPS-DX Deep Trace Debug capabilities provide software developers extra debug and trace capabilities for a more efficient root cause analysis . The system operates at real time performance enabling testing of scenarios with high bandwidth, real-world interactions.