Build Your Interface IP Expertise

We've collected the best Interface IP webinars, videos, and white papers in one place to help you enhance your knowledge about the latest protocols and standards. Whether your chip design includes artificial intelligence capabilities, targets next-generation cars, or enables massive data in the cloud, the DesignWare Interface IP University resources will help you create the SoC your market needs.

WEBINARS

VIDEOS

EVENT PRESENTATIONS

Automotive-Qualified IP for Evolving Integrated ADAS Domain Controller SoCs

In this presentation, our Automotive IP expert explains today's ADAS SoC market trends, the different IP blocks that designers are incorporating into such SoCs, and functional safety and reliability requirements that apply to IP and SoCs for ADAS applications. 

 

The Evolution of High-Speed SerDes PHY IP for High-Performance Computing & Networking SoCs

This presentation describes the key high-speed SerDes PHY requirements for long-reach connectivity that designers need to accelerate their 400G/800G high-performance SoC designs. Hear how Synopsys' DesignWare 112G High-Speed SerDes PHY IP exceed jitter and interference tolerance specifications and can be easily integrated into dense SoCs. 

WHITE PAPERS

Industrial IoT Opportunities in Semiconductors
The growth in semiconductor designs for industrial IoT is driven by several trends including AI integration, safety and reliability, connectivity, throughput, and security. This white paper explains these trends and highlights the required IP that solves the critical problems facing the rapidly changing IoT environment.

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software
This white paper explains how to characterize PCIe 5.0 PHY designs to avoid issues such as signal integrity and reliability prior to manufacturing. This whitepaper also describes Synopsys' post processing techniques for testing the following key transmitter parameters at 32 GT/s: 1. Jitter 2. Spread Spectrum Clocking (SSC).

USB4: User Expectations Drive Design Complexity
This white paper outlines the capabilities of USB4 Hosts, Hubs, Docks, and Devices with an emphasis on how end-user expectations drive the complexity of USB4 products. USB4 is the most complex USB specification so far and requires designers to understand the USB4, USB 3.2, USB 2.0, USB Type-C®, and the USB Power Delivery specifications. Designers must also understand PCIe® and DisplayPort specifications, as well as High Definition Content Protection (HDCP) for many USB4 designs.

Testing PCI Express® 5.0 PHY Receiver Performance in the Absence of a Controller
This white paper describes a methodology for jitter tolerance testing without using the controller to negotiate a link. In addition, the paper outlines a procedure for calibrating the stressed eye representing the worst-case loss characteristics, and shows the jitter tolerance testing of the Synopsys PHY by using the Pattern Matching capability.

LPDDR4/4X DRAM Variants and Possible System Configurations
This whitepaper explains the various available LPDDR4/4X DRAMs and outlines the different possible system configurations with such DRAMs and concludes with a Signal Integrity (SI) based analysis with results for different C/A and DQ bus loads at various data-rates. 

Which DDR SDRAM Memory to Use and When
Selecting the right memory solution is often the most critical decision for obtaining the optimal system performance. This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

USB 3.2: The Latest USB Type-C Challenge for SoC Designers
This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the latest USB 3.2 specification for USB Type-C™, and explains how the latest specification affects speed using USB Type-C connectors and cables. Additionally, the white paper discusses USB 3.2 implementation, the new features of USB 3.2, and how designers can successfully integrate USB 3.2 IP in their next design.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet
This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, even at high-speeds beyond 10Gbps.

Assessing ESD Sensitivity of Interface IP Using Charged Device Model
This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM qualification phase.