DesignWare Interface IP University
USB4: User Expectations Drive Design Complexity
This white paper outlines the capabilities of USB4 Hosts, Hubs, Docks, and Devices with an emphasis on how end-user expectations drive the complexity of USB4 products. USB4 is the most complex USB specification so far and requires designers to understand the USB4, USB 3.2, USB 2.0, USB Type-C®, and the USB Power Delivery specifications. Designers must also understand PCIe® and DisplayPort specifications, as well as High Definition Content Protection (HDCP) for many USB4 designs.
Testing PCI Express® 5.0 PHY Receiver Performance in the Absence of a Controller
This white paper describes a methodology for jitter tolerance testing without using the controller to negotiate a link. In addition, the paper outlines a procedure for calibrating the stressed eye representing the worst-case loss characteristics, and shows the jitter tolerance testing of the Synopsys PHY by using the Pattern Matching capability.
LPDDR4/4X DRAM Variants and Possible System Configurations
This whitepaper explains the various available LPDDR4/4X DRAMs and outlines the different possible system configurations with such DRAMs and concludes with a Signal Integrity (SI) based analysis with results for different C/A and DQ bus loads at various data-rates.
Which DDR SDRAM Memory to Use and When
Selecting the right memory solution is often the most critical decision for obtaining the optimal system performance. This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
USB 3.2: The Latest USB Type-C Challenge for SoC Designers
This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the latest USB 3.2 specification for USB Type-C™, and explains how the latest specification affects speed using USB Type-C connectors and cables. Additionally, the white paper discusses USB 3.2 implementation, the new features of USB 3.2, and how designers can successfully integrate USB 3.2 IP in their next design.