DesignWare IP University: Cloud Computing

WEBINARS

VIDEOS

EVENT PRESENTATIONS

The Evolution of High-Speed SerDes PHY IP for High-Performance Computing & Networking SoCs

This presentation describes the key high-speed SerDes PHY requirements for long-reach connectivity that designers need to accelerate their 400G/800G high-performance SoC designs. Hear how Synopsys' DesignWare 112G High-Speed SerDes PHY IP exceed jitter and interference tolerance specifications and can be easily integrated into dense SoCs. 

 

WHITE PAPERS

Testing PCI Express® 5.0 PHY Receiver Performance in the Absence of a Controller
This white paper describes a methodology for jitter tolerance testing without using the controller to negotiate a link. In addition, the paper outlines a procedure for calibrating the stressed eye representing the worst-case loss characteristics, and shows the jitter tolerance testing of the Synopsys PHY by using the Pattern Matching capability.

LPDDR4/4X DRAM Variants and Possible System Configurations
This whitepaper explains the various available LPDDR4/4X DRAMs and outlines the different possible system configurations with such DRAMs and concludes with a Signal Integrity (SI) based analysis with results for different C/A and DQ bus loads at various data-rates. 

Which DDR SDRAM Memory to Use and When
Selecting the right memory solution is often the most critical decision for obtaining the optimal system performance. This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

A Dual-Mode Error-Correcting Code Solution for 50Gbps Ethernet
This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, even at high-speeds beyond 10Gbps.

Assessing ESD Sensitivity of Interface IP Using Charged Device Model
This white paper describes the CDM ESD event and explains how IC designers can obtain actual CDM voltage levels of an SoC using the peak current level measured during the interface IP CDM qualification phase.