IP for Low-Cost Applications Processor Designs


The applications processor is the heart of low-cost mobile designs. It is responsible for the operating system, applications, display, audio and cellular communications. It is also the interface to wireless combination/companion chips, and other application-specific chips. Pressure to reduce cost often drives higher levels of integration in low-cost application processors, resulting in many market-specific derivatives that need to be designed rapidly and reliably. 

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Low-Cost Applications Processor Diagram

Low-Cost Application Processor Designs

Low-cost application processor designs typically incorporate multicore CPUs, graphics engines, DDR/LPDDR interfaces, audio subsystems, the cellular modem, and medium to high-speed off-chip interfaces. Synopsys’ silicon-proven DesignWare® IP supporting a wide range of mainstream protocols in cost-effective process technologies helps designers develop low-cost applications processors with less risk. 


Synopsys provides a range of DesignWare IP that helps address design requirements of low-cost application processors including the following:

  • Low latency, low-power DDR/LPDDR memory controllers and PHYs supporting LPDDR2, LPDDR3, DDR3, DDR3L (with upgrade path to other memories) optimized to share main memory between CPUs, graphics, and other applications
  • MIPI D-PHY with very low mw/GHz that provide the physical interface for power-optimized, high-speed inter chip communication and an upgrade path to MIPI M-PHY for up to 5.8 Gbps
  • USB High-Speed Inter-Chip (HSIC) controller and PHY enables mid-range inter-chip communications with an upgrade path to faster protocols such as USB SuperSpeed Inter-Chip (SSIC) that use the MIPI M-PHY physical layer
  • A broad range of MIPI controllers connect to Displays (DSI), Cameras (CSI), Storage (UFS), Baseband ICs (DigRF), and other common mobile device components
  • USB 3.0 and USB 2.0 controllers and PHYs enable fast synching and data transfer from mobile devices to host computers and storage
  • HDMI Controllers and PHYs operate up to 6 Gbps per lane allowing 4K Ultra-High Definition video up to 60 FPS with low power
  • Low latency embedded memories right-sized for L1 and L2 cache
  • Embedded memories and logic libraries enable designers to achieve the maximum performance with the lowest possible power consumption for specific application requirements
  • Analog-to-digital and digital-to-analog data converters interface to analog chips and RFICs