IP for High-End Applications Processor Designs


The applications processor is the heart of high-end mobile designs. It is responsible for the operating system, applications, display and audio. It is also the interface to the baseband IC, wireless combination/companion chips, and other application-specific chips. 

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High-End Application Processor Designs

High-end application processor designs typically incorporate multicore CPUs, graphics engines, DDR/LPDDR interfaces, audio subsystems, and high-speed off-chip interfaces. Synopsys enables designers to shorten their design cycles and reduce integration risk by providing a wide range of proven IP solutions for advanced protocols in the latest process technologies. 


Synopsys provides a range of DesignWare IP that addresses design requirements of high-end application processor chips including the following:

  • Low latency, low-power DDR/LPDDR memory controllers and PHYs optimized to share main memory between CPUs, graphics, and other applications
  • Multi-lane, multi-geared interfaces for MIPI D-PHY and MIPI M-PHY operating up to 5.8 Gbps with very low mw/GHz that provide the physical interface for power-optimized, high-speed inter-chip communication
  • USB 3.0 SuperSpeed Inter-Chip (SSIC) protocol that use the MIPI M-PHY physical layer for inter-chip communication
  • A broad range of MIPI controllers that connect to Displays (DSI), Cameras (CSI), Storage (UFS), Baseband ICs (DigRF), and other common mobile device components
  • USB 3.0 and USB 2.0 controllers and PHYs enable fast synching and data transfer from mobile devices to host computers and storage
  • HDMI controllers and PHYs operating at up to 6 Gbps per lane allowing 4K Ultra-High Definition video up to 60 FPS with low power
  • SATA 6G host controller and PHY provides lower latency and higher bandwidth data transfers for notebooks and enables low-power operation
  • Low latency embedded memories right-sized for L1 and L2 cache
  • Embedded memories and logic libraries enable designers to achieve the maximum performance with the lowest possible power consumption for specific application requirements
  • Analog-to-digital and digital-to-analog data converters interface to analog chips and RFICs