Cloud native EDA tools & pre-optimized hardware platforms
Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.
112G Ethernet PHY IP enables true long reach channels for up to 800G high-performance computing SoCs
56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications
Die-to-Die PHY IP enables up to 112G XSR connectivity
Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols
PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes
Webinar: Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges
Webinar: PCIe 6.0 From IP to Interconnect in High-Performance Computing
Webinar: Keeping Latency to a Minimum with 400G/800G Ethernet IP
Webinar: Achieving Low Latency Die-to-Die Connectivity Using a Single Controller and PHY IP Solution
Webinar: PCI Express 6.0 Design Considerations & IP Implementation
Whitepaper: Evolution of Data Center Networking Technology — IP and Beyond
Synopsys 112G Ethernet IP Interoperating with Optical Components & Equalizing E-O-E Link
Synopsys PCIe 6.0 IP TX and RX Successful Interoperability with Keysight
5-nm DesignWare Multi-Protocol 112G PHY IP Long-Reach Demo
DesignWare 112G Ethernet IP ELR Performance & Xtalk Impact on BER
Successful 112G PAM-4 System Interoperability Between Synopsys IP and Samtec Channel
Synopsys IP Passes PCIe 5.0 Compliance and Makes Integrators List
Synopsys IP Achieves Broad Industry Adoption on TSMC's N5 Process
Synopsys Completes Acquisition of MoreThanIP
Silicon-Proof of 112G Ethernet PHY IP in 5nm Process
IP for GF 12LP+ Targeting Cloud Computing and Edge AI SoCs
Chelsio Adopts DesignWare 56G Ethernet PHY IP for HPC Design