Reap the rewards and safely migrate to PCIe 5.0 with DesignWare IP. Dozens of early adopters have already done so, with several successful tape-outs and multiple designs in silicon. Visit the Synopsys booth to see the complete DesignWare Controller, PHY, and Verification IP Solution and network with experts. Also see partner demos enabled by Synopsys DesignWare IP for PCIe 5.0. See full event details.
- End-to-End System with DesignWare IP for PCIe 5.0 at 32GT/s
- Best PPA with DesignWare PHY IP for PCIe 5.0 at 32GT/s
- Verification Closure with PCIe 5.0 IP/VIP & Test Suites
*Israel & Asia Pacific Tour
See demos enabled by DesignWare IP for PCIe 5.0 in Anritsu, Keysight, Samtec, Teledyne LeCroy booths.
*Israel, Amsterdam, Asia Pacific Tour
PCIe Architectures for Chip-to-Chip Interconnects
This presentation will help designers answer questions about their need for root, endpoint, or switch ports and provide guidance on addressing schemes, protocol features, and other options to enable various topologies.
Israel: September 10, 2019 @ 1:00 PM
Amsterdam: September 13, 2019 @ 1:00 PM
Asia Pacific Tour: TBD