Reap the rewards and safely migrate to PCIe 5.0 with DesignWare IP. Dozens of early adopters have already done so, with several successful tape-outs and multiple designs in silicon. Visit the Synopsys booth to see the complete DesignWare Controller, PHY, and Verification IP Solution and network with experts. Also see partner demos enabled by Synopsys DesignWare IP for PCIe 5.0. See full event details.
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PCI-SIG Developers Conferences
Israel, Europe, and Asia Pacific Tour
September 9-10, 2019
Tel Aviv, Israel
September 12-13, 2019
Amsterdam, Netherlands
October 23, 2019
Tokyo, Japan
October 28-29
Taipei, Taiwan
Event for PCI-SIG member companies
Synopsys Demos
- End-to-End System with DesignWare IP for PCIe 5.0 at 32GT/s
- Best PPA with DesignWare PHY IP for PCIe 5.0 at 32GT/s
- Verification Closure with PCIe 5.0 IP/VIP & Test Suites
*Israel & Asia Pacific Tour
Partner Demos
See demos enabled by DesignWare IP for PCIe 5.0 in Anritsu, Keysight, Samtec, Teledyne LeCroy booths.
*Israel, Amsterdam, Asia Pacific Tour
Synopsys Presentation
PCIe Architectures for Chip-to-Chip Interconnects
This presentation will help designers answer questions about their need for root, endpoint, or switch ports and provide guidance on addressing schemes, protocol features, and other options to enable various topologies.
Israel: September 10, 2019 @ 1:00 PM
Amsterdam: September 13, 2019 @ 1:00 PM
Asia Pacific Tour: TBD