Reap the rewards and safely migrate to PCIe 5.0 with DesignWare IP. Dozens of early adopters have already done so, with several successful tape-outs and multiple designs in silicon. Visit the Synopsys booth to see the complete DesignWare Controller, PHY, and Verification IP Solution and network with experts. Also stop by Synopsys' and partners' technical presentation sessions. See full event details.
DesignWare IP Demos
End-to-End System with DesignWare IP for PCIe 5.0 at 32GT/s
Accelerate Verification Closure with PCIe 5.0 IP/VIP & Test Suites
PCIe 5.0 Interop Success with DesignWare IP & Marvell Test Chip
Best PPA with DesignWare PHY IP for PCIe 5.0 at 32GT/s
PCIe 5.0 interop success with DesignWare IP & Intel Test Chip
Enter to Win!
See three demos in the Synopsys booth for a chance to win a Sonosphear Bluetooth Speaker.
Drawing at 6:15pm Tuesday, June 18 & 1:00pm Wednesday, June 19.
Must be present to win.
See additional DesignWare IP for PCIe 5.0 demos with partners: Anritsu, Keysight, Samtec, Teledyne LeCroy, Tektronix
Comparing PCIe Solutions for Emulation and Simulation
This session will present the conceptual and implementation details of different PCIe emulation solutions and compare them with each other, with the traditional PCIe Simulation Verification (VIPs) and Design IP solutions.
Tuesday, June 18, 2019 @ 3:30 PM
PCIe Architectures for Chip-to-Chip Interconnects
This presentation will help designers answer questions about their need for root, endpoint, or switch ports and provide guidance on addressing schemes, protocol features, and other options to enable various topologies.
Wednesday, June 19, 2018 @ 10:30 AM
Accurate End-to-End PCIe 5.0 System Modeling
This paper will explain how to design a PCIe 5.0 system that has predictable performance, is optimized for cost, and offers shorter design and verification cycle times. The paper will also demonstrate system correlation and measurement for validating this proposed PCIe 5.0 system solution.
Tuesday, June 18, 2019 @ 9:30 AM
32GT/s Test Platform for AI and ML Implementations
This presentation introduces a AI interconnect test platform for silicon I/O stress testing, and traces through the 32GT/s SI optimization process. The optimization is reviewed for a cabled interconnect including sidebands plus 1 and 2 connector PCB topologies. Channel simulations and measurements are included.