DesignWare IP for PCI Express (PCIe) 6.0

Overview

Synopsys’ DesignWare IP for PCI Express (PCIe) 6.0 complete solution, operating at 64 GT/s data rates, enables real-time data connectivity with low-latency and high-throughput for high-performance computing, storage, and AI SoCs. The complete solution encompasses controller, PHY, and verification IP.

Leveraging decades of engineering expertise to develop robust IP solutions for PCIe through all the generations of the specification, Synopsys’ DesignWare IP complete solution for PCI Express (PCIe) 6.0 is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, and more to allow a seamless migration to PCIe 6.0 designs. 

DesignWare Controller and PHY IP for PCIe 6.0

See a demo of Synopsys’ complete IP solution for PCIe 6.0 technology showing the controller operating at 64GT/s in FLIT mode and the PAM-4 PHY in 5-nm process achieving two orders of magnitude better BER with 32dB PCIe channel.

Successful PCI Express 6.0 Designs at 64GT/s with IP

How PCI Express 6.0 Can Enhance Bandwidth-Hungry High-Performance Computing SoCs

PCIe 6.0 Doubles Speed with New Modulation Technique