The New Frontier of Die-to-Die Interface IP: What You Need to Know for Silicon Success

In this webinar our SVP, John Koeter, summarizes the market trends and die-to-die use cases for high-performance computing (HPC) SoC designs. Our product expert, Manmeet Walia, follows by taking a deeper look into advantages of using 112G SerDes-based USR/XSR IP and parallel-based HBI IP for die-to-die connectivity. Manmeet explains how the use of our IP allows trade-offs between critical metrics like latency, power, and bandwidth per beachfront to meet the specific requirements of HPC designs. 

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John Koeter, SVP of Marketing and Strategy for IP

John Koeter joined Synopsys in 1998 and is currently Senior Vice President of Marketing and Strategy for IP. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices.

Manmeet Walia, Sr. Product Manager for High-Speed SerDes PHY IP

Manmeet Walia brings over 18 years of experience in product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and an MBA from San Diego State University.