Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

In this webinar, our SVP, John Koeter, highlights the market trends and use cases for high-performance computing (HPC) SoCs. Our product expert, Gary Ruggles follows by outlining the considerations designers must make when moving to PCI Express (PCIe) 5.0 designs. Gary also explains some of the key advantages of CXL including cache coherency and latency, and describes the different CXL types for HPC designs. 

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John Koeter, SVP of Marketing and Strategy for IP

John Koeter joined Synopsys in 1998 and is currently Senior Vice President of Marketing and Strategy for IP. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices.

Gary Ruggles, Sr. Product Manager for PCIe & CXL

Gary Ruggles brings over 25 years of experience in electronics and integrated circuit design. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing.