DesignWare Die-to-Die PHY IP Solutions

MCM Substrate or Silicon Interposer

Overview

Synopsys’ DesignWare® Die-to-Die IP solution includes PHYs with leading power, performance, and area, for high-performance computing SoCs targeting hyperscale data center, AI, and networking applications. The PHYs, available in advanced FinFET processes, are architected for high flexibility and configurability, enabling optimized data throughput density up to ~2Tbps/mm of beachfront, regardless of the target packaging technology. The USR/XSR PHY IP leverages high-speed SerDes PHY technology up to 112Gbps per lane for ultra and extra short reach links. The High-Bandwidth Interconnect (HBI) PHY IP, leveraging wide-parallel bus technology, delivers 4Gbps per pin die-to-die connectivity with low latency.

Advances in DesignWare Die-to-Die PHY IP

Hear the latest on Synopsys' DesignWare Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP, available in advanced FinFET processes, addresses the power, bandwidth, and latency requirements of high-performance computing SoCs targeting hyperscale data center, AI, and networking applications.