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VC Verification IP for USB
Synopsys® VC Verification IP for USB provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of USB Hosts, Devices and Hubs with support for Super Speed, High speed, and Full Speed, Extended Super Speed, and Low Speed modes.
VC VIP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the need for language translation wrappers that affects performance and ease-of-use. VIP can be integrated, configured and customized easily with minimal effort. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage, example tests and comprehensive collection of sequences.
Highlights
- Native SystemVerilog/UVM
- Source code Test Suite (Optional)
- Runs on all major simulators
- Built-in verification plan and coverage
- Extensive protocol checks
- Verdi integrated protocol-aware debug
- Debug ports
- Error injection and exceptions
Key Features
- USB4 (EA)
- USB 3.2, 3.1, 3.0, 2.0
- eUSB2 Native and Repeater modes
- On-The-Go (OTG) 3.0, 2.0
- Host and Device modes
- Hub model for 3.2/3.1/3.0/2.0
- Protocol Layer
– Bulk, Control, Interrupt and ISOC
– Data Bursting
– SS Bulk Stream
– LMP, SOF and ITP Generation
– USB 2.0 Split - Link Layer
– LTSSM with full control to start in any state
– SS Power Management
– Cable attach and detach
– 2.0 LPM, suspend and resume
– Speed Fall-back and Fall-forward
– Test Mode - Physical Layer
– ESS PIPE3, ESS PIPE4, ESS serial
– USB 2.0 Serial and HSIC with clock recovery
– UTMI, ULPI, SSIC Serial, SSIC RMMI