Title: Advanced Integrated Development Environment for SoC Design and Verification

Abstract: Two things are certain in chip design and verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. This presentation will highlight the need for an innovative solution and bring the best practices of software development to hardware design and verification with customer case studies from DeepAI and Quantum Machines.

Title: *Datapath Validation Using Formal Techniques

Abstract: CPU, GPU and AI designs are datapath heavy with unique design characteristics and require advanced verification techniques and methodology. These designs have mathematical functions like addition, subtraction, multiplier, square root, and floating-point units (FPU). Verifying these mathematical functions using traditional methods is inefficient, time consuming and impractical. This presentation will highlight the need for an innovative datapath validation solution and share best practices through customer case studies from Samsung and Intel.
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Title: The New Power Perspective – Realistic Workloads – Real Results

Abstract: Have you ever gone through the huge effort of taping out your next-generation SoC only to find out when it’s too late that your design is drawing 30% more power?  Your team was likely disappointed after pushing hard to reduce power by a small percentage, only to realize that the goal was missed by much more.

In this session we will explain why this still happens. We will explore a whole new perspective of possibility for power profiling SoC designs. You will learn about breakthrough emulation technology that enables multiple iterations per day with actionable results in the context of the full SoC design and its software workload. The power profiles can be used by software and hardware designers to identify substantial power improvement opportunities helping to ensure that power targets are met.

Title: Advanced Integrated Development Environment for SoC Design and Verification

Abstract: Two things are certain in chip design and verification: as many bugs as possible must be found and fixed before fabrication, and this must happen as early as possible in the development process. The much-desired “shift left” in verification requires that advanced analysis and debug technologies be available to engineers from the earliest stages of the project. This presentation will highlight the need for an innovative solution and bring the best practices of software development to hardware design and verification with customer case studies from DeepAI and Quantum Machines.