Growing challenges from capacity, variability and complexity need to be managed, so it is necessary to rethink both the algorithmic and infrastructural aspects of clock implementation. IC Compiler II has been re-architected to help meet today's and tomorrow's clock design challenges.
To download this paper, please complete the form below and click the "continue >>" button.
Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.