ASIL B & D Certified IP, AEC-Q100 Reliability, ISO 9001 Certified Quality Management System

Automotive SoC architectures are evolving to support the transition to centralized domain compute modules, complex FinFET processes, artificial intelligence (AI) capabilities, and new Advanced Driver Assistance Systems (ADAS) and vehicle-to-everything (V2X) communication.

Synopsys provides the broadest portfolio of automotive-grade Interface, Processor, Security and Foundation IP with highest levels of safety, security, quality and reliability, accelerating SoC-level design and qualification.

<ul>
<li>ASIL B and D Ready IP developed and assessed specifically for ISO 26262 random hardware faults&nbsp;</li>
<li>DesignWare ARC EM22FS processor compliant for both ASIL D random hardware faults and ASIL D systematic</li>
<li>ISO 9001-certified Quality Management System</li>
<li>IP designed and tested as per AEC-Q100</li>
<li>SoC-Level safety manager with enhanced safety packages</li>
<li>Automotive grade 0, 1, and 2 temperature</li>
<li>Available in 22FDX and FinFET processes including 16-nm and 7-nm with 5-nm in development</li>
</ul>

Highlights

  • ASIL B and D Ready IP developed and assessed specifically for ISO 26262 random hardware faults 
  • ARC EM22FS processor compliant for both ASIL D random hardware faults and ASIL D systematic
  • ISO 9001-certified Quality Management System
  • IP designed and tested as per AEC-Q100
  • SoC-Level safety manager with enhanced safety packages
  • Automotive grade 0, 1, and 2 temperature
  • Available in 22FDX and FinFET processes including 16-nm and 7-nm with 5-nm in development
ADAS + -
<p>Synopsys’ DesignWare Automotive IP is implemented using a functional safety (FuSa) compliant development flow for ISO 26262 random hardware faults and systematic for ASIL B and D safety levels, helping designers accelerate their ISO 26262 SoC-level functional safety assessments and reach target ASILs.</p>
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Achieving ASIL Targets

Synopsys’ Automotive IP is implemented using a functional safety (FuSa) compliant development flow for ISO 26262 random hardware faults and systematic for ASIL B and D safety levels, helping designers accelerate their ISO 26262 SoC-level functional safety assessments and reach target ASILs.

 

Gateways + -
<p>Synopsys offers a portfolio of silicon-proven IP including up to 10G Ethernet IP supporting time-sensitive networking (TSN) for real-time high-performance data connectivity, ARC processors with ASIL D safety capabilities for real-time data management, and security IP with root of trust for encryption/decryption.</p>
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Achieving Real-Time Data Connectivity, Management, Security

Synopsys offers a portfolio of silicon-proven IP including up to 10G Ethernet IP supporting time-sensitive networking (TSN) for real-time high-performance data connectivity, ARC processors with ASIL D safety capabilities for real-time data management, and security IP with root of trust for encryption/decryption.

 

<p>Synopsys offers USB, LPDDR4, HDMI, MIPI, PCI Express®, Ethernet Time Sensitive Networking (TSN), mobile storage, security, data converters, logic libraries, embedded memories, Sensor and Control IP Subsystem, and ARC® Processors to speed connected vehicle and infotainment SoC development in the latest 28-nm and 16/14-nm FinFET process technologies.</p>
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Enabling Real-Time Multimedia Networks

Synopsys offers USB, LPDDR4, HDMI, MIPI, PCI Express®, Ethernet Time Sensitive Networking (TSN), mobile storage, security, data converters, logic libraries, embedded memories, Sensor and Control IP Subsystem, and ARC® Processors to speed connected vehicle and infotainment SoC development in the latest 28-nm and 16/14-nm FinFET process technologies.

 

<p>Synopsys’ ASIL B and D Compliant IP portfolio is developed and assessed specifically for random hardware faults and ASIL D systematic, accelerating SoC-level functional safety certification.</p>
<p>&nbsp;</p>

Accelerating SoC-Level Functional Safety Certification

Synopsys’ ASIL B and D Compliant IP portfolio is developed and assessed specifically for random hardware faults and ASIL D systematic, accelerating SoC-level functional safety certification.

 

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