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| User Papers and Presentations |
| FA2 User & Tutorial Session - Parallel DRC Cleanup Methodology, ARM Cortex-A72 Implementation in IC Compiler and IC Compiler II, Network-on-Chip Floorplanning |
Parallel DRC Clean-Up Using IC Compiler and Custom Designer (Best Presentation - 1st Place)
Author(s): Nadeem Eleyan, Jeremy Bailey, Curtis Richardson, Patrick Szabo - Qualcomm; Kelly Burleson, Frank Gover - Synopsys |
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| FA3 Synopsys Verification - Improving Test Generation |
Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus
Author(s): Kevin Johnston, Jonathan Bromley - Verilab |
|
Performance of SystemVerilog Sudoku Solver with Synopsys VCS (Best Presentation - 2nd Place)
Author(s): Jeremy Ridgeway - Avago Technologies |
|
Verification of a Cache Coherent System with an A53 Cluster Using ACE VIP with Graph Based Stimulus
Author(s): Galen Blake, Perry Wobil - Altera Corporation |
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| FA4 Synopsys Verification - SoC Configurability, Coverage |
A Vendor-Independent Formal Unreachability Analysis Flow for Automated Coverage Closure
Author(s): Xiushan Feng - NVIDIA; Abhishek Muchandikar, Sunil Keerthi, Praveen Tiwari - Synopsys |
|
Obtaining a Maximally Compressed Verification Test Set
Author(s): James Longino, Mrinal Bose - Samsung Austin R&D Center |
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RTL-Agent Switch - Implementation and Applications
Author(s): Aman Arora, Nathan Wooster, Pavan Mula, Rob Porter - NVIDIA |
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| FA5 NanoTime for Memory; NanoTime for High Performance CPU; SiliconSmart POCV Accuracy & Performance |
NanoTime and SPICE Accuracy Correlation in Advanced Nodes (Best Presentation - 3rd Place)
Author(s): Vibhor Mittal, David Newmark, Teja Singh, Sundar Rangarajan - Advanced Micro Devices |
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SiliconSmart POCV Constraints - Correlation and Performance/Accuracy Exploration
Author(s): Harish Krishnan - Samsung Austin Design Center; Myles Prather - Synopsys |
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Transistor-Level Static Timing Analysis and Characterization of Embedded SRAM Using NanoTime for Memories
Author(s): Clint Parker - Hewlett-Packard; Charles Jiang - Synopsys |
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| FA7 Software Security |
Secrets for Delivering Software - Faster and Cheaper
Author(s): Dhaval Shah - Synopsys |
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| FB2 User & Tutorial Session - IC Compiler II GUI Walkthrough & IC Compiler II Marketing and R&D Update |
IC Compiler II Update
Author(s): JC Lin, Stelios Diamantidis - Synopsys |
|
| FB3 User Session - Advanced UVM |
Global Event Handling with UVM Custom Phasing
Author(s): Jeremy Ridgeway, Dolly Mehta - Avago Technologies |
|
Using a Generic Plug and Play Performance Monitor for SoC Verification
Author(s): Dr. Ambar Sarkar, Bhavin Patel, Janak Patel, Kaushal Modi, Ajay Tiwari - eInfochips |
|
| FB4 User & Tutorial Session - UVM Agents, Verdi Debug |
Mastering Reactive Slaves in UVM (Technical Committee Award)
Author(s): Jeff Montesano, Mark Litterick - Verilab; Taruna Reddy - Independent |
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| FB7 User & Tutorial Session - Systems/Prototyping/FPGA |
SoC Development and Prototype with VDK
Author(s): Taylor Holmes, Andrew Passerelli, John Connor - Northrop Grumman Corporation |
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| FC3 User & Tutorial Session - Do More with VIP, VCS 2015.09 |
Tests Reusability and Portability - A Case Study on Reusing USB IP Level Test Suite at SoC
Author(s): Averroes Umatiya, Amol Bhinge,- Freescale Semiconductor; Karim Aoua - Synopsys |
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| FC4 Tutorial Session - Reducing Memory Footprint, Parameter Verification, Formal |
Finding Incorrect Parameter Settings Early in the Development Phase Using Certitude
Author(s): Varun Ramesh, Amol Bhinge - Freescale Semiconductor; Jay Dutt - Synopsys |
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Optimization Techniques to Improve Simulation Memory Performance
Author(s): Aditya Musunuri, Amol Bhinge- Freescale Semiconductor; Narayana Koduri - Synopsys |
|
| FC7 User & Tutorial Session - Prototyping & Emulation |
Pre-Silicon Stress Testing with Real World Network Traffic Using FPGA-Based Emulation
Author(s): Jaime Castano, Micky Kowlessar - Freescale Semiconductor |
|
| Keynote |
Silicon to Software - Scale Complexity, Systemic Complexity, and Software Complexity
Author(s): Aart de Geus, Chairman and Co-CEO - Synopsys |
