Using "Continuous Integration" Practices for SoC Development

Introduction

Continuous Integration is a software development practice used to improve software quality and reduce deployment risk in every step of the development process – from prototyping through final product deployment. Applying the principles of Continuous Integration to hardware is now a reality, enabling designers to implement the same practices and principles of software development to hardware projects, improving quality and reducing risk.

What is Continuous Integration?

Continuous Integration (CI) was first named and proposed in 1991 as a software engineering practice for merging and integrating all developers’ working copies to a shared mainline several times a day.

The concept has since evolved to automatically build and test after each integration in a continuous cycle of builds so that the integration becomes a non-event. The cycles include developing, building and compilation, executing automated tests and inspections, deploying software and receiving feedback (Figure 1).

At a high level, CI allows software development teams to:

• Reduce risk by integrating software changes many times a day, which facilitates the early detection of defects and measures software health
• Reduce repetitive, manual processes saving time, cost and effort
• Generate deployable software to stakeholders, such as client or users
• Enable project visibility by providing the ability to notice trends and make effective decisions
• Establish greater confidence in the software integrity by using a single-source point to build all software assets

Continuous Integration in Hardware and Software

Prior to the rise of SoC prototyping, hardware and system design could be very risky because feedback would only occur after producing a test chip or even the final SoC. Setting up test environments for hardware projects is time consuming, and if compliance testing is also needed, the setup time is even longer with lots of manual work. This drawn-out process can lead to a lack of consistency in testing.

With physical prototyping, such as HAPS prototyping systems and DesignWare IP Prototyping Kits, designers can start designing and iterating prior to final hardware availability, saving weeks or months of development time.

DesignWare IP Prototyping Kits provide the essential hardware and software elements needed to reduce IP prototyping and integration effort. Implemented on Synopsys HAPS-DX physical prototyping systems, these platforms are used as a proven and complete reference design with validated IP configurations and necessary SoC integration logic and the necessary software drivers for targeting system bring-up, debug and testing.

Using physical prototyping as a co-design environment gives designers an earlier understanding of the impact of design decisions in the system, code and configurations. Decisions can be verified with real world I/Os and hardware, which allows both hardware and software teams to make choices that streamline SoC design and testing. The blurred lines between these two worlds is vanishing due to the adoption of prototyping methodologies and verification flows where hardware and software design are tightly coupled (Figure 2).

SoC Prototyping and Automation Engine

The CI concepts applied to SoC prototyping help bring together the hardware and software as a system, which allows for fast feedback at various stages in the cycle: system development, integration and testing.

To further accelerate system development for software and hardware engineers, IP and prototyping vendors are delivering tools to speed bring-up and help development teams understand the impact of their hardware/software configurations for the final design early in the process – when design changes can still be made.

Today, physical prototyping platforms enable designers to achieve first-silicon success through the use of CI and the ability to get feedback earlier in the design cycle. Using these new tools and platforms provides a clear path for testing configurations at a transaction level and/or provide an actual co-design environment where the code and configuration can be verified on hardware.

To bring together these worlds the choice of an automation engine becomes crucial. The automation engine should be able to access RTL (IP hardware) and software source code, integrate the required tools (RTL synthesis, C code compiler, etc.), deploy them in real hardware platforms like FPGA boards, test the full system and produce reports (Figure 3).

Synopsys Use Case – a CI flow

Synopsys’ internal team responsible for testing and validating the DesignWare Controller IP in a prototyping context faced the challenges that all the hardware validation was done manually, using scripts that were maintained ad-hoc, without the possibility for regression. This resulted in several issues:

• Validation and compliance tests took too long to be completed
• Setting up the test environment was onerous
• No consistency among tests
• No automatic traceability among product version tests
• Inefficient HW/SW testing processes
• Ineffective reporting transparency outside of immediate workgroup

To improve software and hardware integration during the development stage, Synopsys developed and deployed a CI system to combine and accelerate the deployment of hardware and software.

The Synopsys team used DesignWare IP Prototyping Kits as the platform to test their new automation process and the core platform to deploy the automation engine. The kits center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic such as clock, reset, power management, and test logic for a specific IP protocol, implemented on Synopsys' HAPS-DX physical prototyping system. The kits are an ideal platform for the Synopsys team to learn how to create and follow basic principles in IP testing and validation projects:

• Automate everything
• Discover issues early in both hardware and software

Setting up a flow to bring CI to hardware and software allows for testing to start earlier, reduced testing costs and time in the testing phase. The flow shown in figure 4 allows Synopsys teams to test and validate not only the digital design but also the hardware validation design, software implementation and the whole system instantiated in the FPGA: