Technical Series: AI Edition

Join Synopsys’ Chekib Akrout, VP strategic programs, and other Synopsys experts to learn what’s new in AI SoC design through five lenses: industry trends, verification, prototyping, IP, and implementation.


Date:     Monday April 29, 2019
Time:    10:00 a.m. to 5:00 p.m.
Location: ventureLAB, 3600 Steeles Ave E, Markham, Ontario, Canada

*Registration is required for attendance


10:00-10:10         Welcome & Opening Remarks
10:10-11:00         AI Design and Drivers of AI Chip Architectures
11:00-11:10         Break
11:10-12:00         Efficient Architecture Optimization, Verification, and and Early Software Development for AI SoCs
12:00-1:00           Lunch will be provided
1:00-1:50             Using HAPs Prototyping Solutions to Perform HW/SW Validation for Complex AI SoCs
2:00-2:50             Nurturing Next Gen AI SoCs with IP
3:00-3:50             AI Chip Physical Implementation from the Data Center to the Edge
4:00-4:05             Wrap-up
4:05-5:00             Meet & Greet


AI Design and Drivers of AI Chip Architectures

Chekib Akrout; Corp VP, Strategic Programs

Chekib Akrout sets the stage for our day by sharing his analysis and AI marketplace trends that are driving Synopsys’ strategies for helping customers bring intelligent computing from specification to products.

You’ll learn:

  • The challenges and opportunities presented by AI
  • Present AI chip architectures and the drivers for creating new ones
  • How these trends are converging

Efficient Architecture Optimization, Verification, and Early Software Development for AI SoCs
Asheesh Khare; Director, Applications Engineering

If you’re involved in architectural exploration for AI accelerators, you won’t want to miss Asheesh Khare’s presentation about optimization and early software development. Asheesh discusses the importance of choosing the right methodology to optimize software and the hardware for both PPA (power, performance, and area) and TTM (time-to-market) targets.

You’ll learn:

  • How Synopsys’ Verification Continuum solutions address the specific need of AI SoCs
  • How customers use Platform Architect for both power and performance optimization
  • How using Virtualizer/VDKs assists in early software development and test


Using HAPS Prototyping Solutions to Perform HW/SW Validation for Complex AI SoCs 

Rick Furtner; Applications Engineer, Sr Staff
Kris Dobecki; Applications Engineer

In this presentation and demonstration, you’ll get a glimpse at how to use HAPS® FPGA-based prototyping to quickly validate and debug complex neural network and vision processing system that includes an ARC® EV61 SIMD image processing core and its 880 MAC/cycle CNN accelerator.
You’ll see how you can use a HAPS system to:

  • Validate and debug both RTL and software
  • Run simultaneous sparse optical flow and neural network graphs in milliseconds instead of hours


Nurturing Next Gen AI SoCs with IP

Ron Lowman; Product Marketing Manager, Staff

Innovations in deep learning algorithms and neural network processing is driving new technology requirements for SoCs. Ron Lowman shares his thoughts on addressing the unique needs of AI SoCs, from current market trends, the basics of IP selection and how expertise leads to optimized designs.

You’ll learn:

  • AI SoC’s IP trends based on application requirements
  • How key challenges in processing, memory, and connectivity are tackled for next generation AI SoC designs
  • How nurturing IP implementations during the design process are enhancing AI SoCs with proficiency, experience, and tools


AI Chip Physical Implementation from the Data Center to the Edge 
Stelios Diamantidis; Director, AI Products, DG

More than half of all chipset will include AI acceleration capabilities just six years from now by the end of 2025. Stelios Diamantidis wraps up our day with a discussion of how AI architectures present new challenges to physical designers and how Synopsys’ Fusion Design Platform is addressing them.

You’ll learn:

  • How trends in data center and edge AI accelerators are driving chip designs
  • The physical implementation implications of new processing architectures
  • AI chip acceleration technologies within the Fusion Design Platform that address these AI challenges