Tech Insights 2020

October 6 - 7, 2020
Virtual Experience

Why Attend?

Synopsys is hosting a virtual event, Tech Insights 2020, focusing on critical aspects for state-of-the-art designs at emerging and established nodes. This event provides an opportunity for users to stay connected with the latest products and innovations. Synopsys technical experts will provide an “under the hood” look at proven and new technologies that designers can use to meet their aggressive time schedules and to achieve challenging Performance, Power and Area goals. Multiple sessions will be offered covering hot topics including Automotive, Verification Hardware & Software, IP and Analog Design & Simulation.

Who Should Attend?

Engineers working with chip design and verification using Synopsys technologies and IPs, who want to keep up with the latest innovations and features for their state-of-the-art designs, and mindful of time to market constraints. 

Agenda-At-A-Glance

Joachim Kunkel

General Manager, Solutions Group, Synopsys

Tuesday, October 6 | 9:30 a.m. - 10:15 a.m. CEST

Semiconductor Industry Trends and IP Perspectives

Joachim Kunkel will share his perspective on the Semiconductor Industry by market segment, focusing on Automotive, Security, Machine Learning, Networking, Communication and Processor, and related IP trends for these markets.

Day One: Tuesday, October 6


Automotive

11:15 a.m. - 12:45 p.m. CEST

The Automotive track covers a range of topics that are essential for Automotive SoC designers to achieve quality-of-results (QoR) and satisfy ISO 26262 functional safety requirements while reducing overall effort and impact on the development schedule. In this track we present Synopsys’ comprehensive automotive design flow and an example based on a Synopsys ARC functional safety processor. We will introduce how TestMAX FuSa performs fast static analysis early in the design flow to identify and address design areas with highest probability of causing functional safety failures. We conclude the session with a presentation by GLOBALFOUNDRIES 22FDX™ Automotive Grade 1 design platform.

Tuesday, October 6 | 11:15 a.m. - 12:00 p.m. CEST

Synopsys’ Comprehensive Automotive Design Flow for Autonomous Driving and ADAS Applications

Description: The ISO 26262 standard defines functional safety (FuSa) requirements to achieve the target automotive safety integrity level (ASIL) for applications such as autonomous driving and advanced driver assistance systems (ADAS). Key objectives for an automotive SoC design project are to optimize power-performance-area (PPA) in the presence of safety mechanisms and reduce overall effort and impact on the development schedule. Synopsys’ comprehensive automotive design flow provides a unified FuSa verification solution with automated FMEA and FMEDA, early functional safety analysis, and a unified fault campaign for measured FMEDA to confirm that target ASIL is met. Synopsys’ new native RTL-to-GDSII solution, driven by FuSa intent, insures that safety mechanisms are implemented per design specification. This presentation describes the comprehensive automotive design flow and an example based on a Synopsys ARC functional safety processor.

Stewart Williams

Senior Automotive Vertical Marketing Manager, Design Group, Synopsys

Speaker: Stewart Williams is Senior Automotive Vertical Marketing Manager in the Design Group at Synopsys where he leads the automotive solutions encompassing Digital Implementation, Test, Signoff, and Custom Design. Prior to his current role, Stewart was Senior Technical Marketing Manager for Synopsys’ flagship place & route product. Before joining Synopsys, he managed the product engineering team for parasitic extraction at Cadence Design Systems. Stewart received his bachelor’s degree in Electrical Engineering from Virginia Tech in 1993, and M.S. and Ph.D. degrees in Electrical and Computer Engineering from North Carolina State University in 1995 and 1999, respectively. 

Tuesday, October 6 | 12:00 p.m. - 12:20 p.m. CEST

Addressing Functional Safety Issues Early and Cost Effectively!

Description: Automotive systems have stringent functional safety requirements as defined by the ISO 26262 standard. To meet the target Automotive Safety Integrity Level (ASIL), designers face the challenge on how many redundant structures to add with minimum area and cost penalty. Another challenge is completing the assessment late as it leaves too little time to make changes to the design. This presentation will show how Synopsys TestMAX FuSa uses static analysis early in the design flow either at RTL or Gate netlist to calculate ISO 26262 metrics such as Single Point Fault Metric (SPFM) and Diagnostic Coverage. TestMAX FuSa identifies modules in the design that have the highest probability of causing functional safety failures and provides guidance to achieve the target ASIL.

Frank Nolting

Applications Engineer, Design Group, Synopsys

Speaker: Frank Nolting studied at the Technical University of Kaiserslautern in Germany and graduated with a master degree in electrical engineering and computer science. Frank worked at Infineon before he joined Synopsys in 2001. Since then he supports all Synopsys DFT tools as an Applications Engineer.

Tuesday, October 6 | 12:20 p.m. - 12:45 p.m. CEST

GF 22FDX™ AG1 Automotive Design Platform

Description: The presentation introduces GLOBALFOUNDRIES 22FDX™ as the technology and design platform of choice for the next generation of automotive designs. 22FDX™ is qualified for Automotive Grade 2 and 1 application profiles. Especially Automotive Grade 1(AG1) requires a specific design methodology composing GFs AG1 PDK components, Synopsys AG1 foundational IP like standard cell libraries, AG1 margins for reliability and design robustness, and Synopsys’ digital implementation tools and flows into a consistent and tape-out proven design platform. The presentation focuses on design guidelines for AG1 reliability (aging), high sigma design and additional margining. The presentation also summarizes the features of GLOBALFOUNDRIES’ digital reference flows using Synopsys’ DesignCompiler, IC Compiler II and IC Validator.

Ulrich Hensel

DMTS Design Enablement, GLOBALFOUNDRIES

Speaker: Ulrich Hensel is driving design methodology topics from the very beginning of GLOBALFOUNDRIES in 2009. He has covered Place and Route technology files and flows, design for manufacturing, digital implementation and sign-off flows, benchmarking, design guidelines, margining, and reliability. He has been focusing on GLOBALFOUNDRIES FDX™ technologies including, since 2018, automotive design enablement. Before GLOBALFOUNDRIES was formed out of AMD, Ulrich worked in several digital design and design verification roles contributing to wireless communication, southbridge, northbridge and PCIE designs. He received his Diploma and Doctorate degree in Computer Science from the University of Technology in Dresden.

Analog Custom Design

11:15 a.m. - 12:35 p.m. CEST

The Synopsys Custom Design Platform includes breakthrough technologies in Simulation, Reliability Analysis, Analog Design Closure, Layout Automation and Signoff. In this track, we will explain several of the key innovations that thousands of analog and mixed-signal designers are using it daily to deliver new designs at an unprecedented pace.

Tuesday, October 6 | 11:15 a.m. - 12:15 p.m. CEST

Reimagining Analog Design and Layout - Why Custom Compiler is Proven to be a Better Alternative

Description: This presentation will introduce several novel analog design and layout productivity innovations in Custom Compiler that Synopsys uses to deliver 100’s of analog and mixed-signal IPs each year. Traditional analog design flows don’t provide required automation and productivity gain especially when compared to the advances made for digital SoC design. On the other hand, the effort needed to develop and close analog layout has increased significantly because of challenges like variability, and design rule complexity, impact of parasitics, reliability requirements, etc. Synopsys Custom Compiler accelerates the creation of analog layout through innovations in custom layout automation and integrates industry standard analysis and signoff capabilities to drive rapid design closure. We will demonstrate how Custom Compiler’s visually-assisted layout automation tightens communication between design and layout teams and reduces overall layout time. We will also show how Custom Compiler’s Extraction Fusion technology with StarRC enables designers to extract parasitics from partially completed layout – without needing to finish the design and run LVS.

Dave Reed

Senior Director, Design Group, Synopsys

Speaker: Dave Reed is Senior Director of Custom Design Product management at Synopsys. He has been involved in IC design and electronic design automation for more than 35 years, with a focus on analog and custom design. Prior to Synopsys Dave was co-founder and CEO of Blaze DFM, which helped engineers overcome design challenges of advanced process nodes.  

Tuesday, October 6 | 12:15 p.m. - 12:35 p.m. CEST

Design of CMOS Image Sensors with Custom Compiler

Description: IMASENIC develops CMOS image sensor products for a variety of applications. The performance of the analogue signal conditioning electronics, from the pixel to column-parallel analogue-to-digital converters is crucial for the quality of the products. Thanks to the Custom Compiler environment and the other AMS tools from Synopsys we can achieve first-time right designs even for complex sensors.

Adria Bofill Petit

Cofounder & CTO, IMASENIC

Speaker: Adria Bofill Petit is cofounder and CTO of IMASENIC. The company was established in 2017 to design and supply custom CMOS image sensors. Adria holds a MEng in Telecommunications and Electronics (ETSETB TelecomBCN, Barcelona, Spain, 1998), a Diploma of Advanced Studies in Microelectronics (Université Joseph Fourier, Grenoble, France, 1999), and a Ph.D. in Electronics Engineer (The University of Edinburgh, Edinburgh, UK, 2004). During his doctorate, in 2001 he worked for the company Cadence Design Systems in the design and verification of PLLs (Phase-Locked Loops). After his PhD, Adrià worked at Analog Devices (UK) as a senior engineer in IC power management. In 2006, he started working for the start-up Gigle Networks where he was one of the engineers in charge of the design of the analog front-end of power-line communications systems (PLC). Gigle was acquired by Broadcom at the end of 2010. Within Broadcom Adria was the Engineering Manager of the analog and mixed-signal IC design group of the Barcelona office. His team designed integrated circuits for audio, power management and front-end communications systems for PLC products (power-line communications) and smart-phones for the leading consumer electronics companies worldwide. 

Long Reach Performance and Reliable Die-to-Die Links

11:15 a.m. - 12:15 p.m. CEST

Learn about different use cases and selection criteria for high-speed SerDes PHY IP in high-performance computing SoCs including 112G/56G Ethernet PHY IP for true long reach performance and die-to-die connectivity for HBI and 112G USR/XSR links. 

Tuesday, October 6 | 11:15 a.m. - 12:15 p.m. CEST

Ensuring True Long Reach Performance and Reliable Die-to-Die Links in 800G Hyperscale Data Center SoCs

Description: Demand for real time connectivity in hyperscale data center SoCs is growing significantly due to complicated heterogenous workloads that require massive parallel processing, thus leading to explosion of machine-to-machine traffic. In addition, as SoCs reach reticle sizes, designers are splitting the SoC into multiple dies that are then assembled in the same package, requiring reliable die-to-die connectivity. This session highlights the different use cases for high-speed SerDes IP and describes the different considerations that go into selecting the optimal 112G/56G Ethernet PHY IP for true long reach performance. This session also explains how designers can leverage SerDes-based PHY for 112G USR/XSR links and parallel-based HBI to meet their multi-chip module design needs. 

Manmeet Walia

Senior Product Manager, Solutions Group, Synopsys

Manuel Mota

Product Marketing Manager, Solutions Group, Synopsys

Speaker: Manmeet Walia is a Senior Product Manager for Mixed-Signal PHY IP at Synopsys. He brings more than 18 years of experience in product marketing, product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and a MBA from San Diego State University.      

Speaker: Manuel Mota joined Synopsys in 2009 as a Product Marketing Manager and is responsible for the DesignWare Data Converter, High-Speed SerDes, and Bluetooth IP product lines. He brings more than 18 years of technical and marketing experience to his position. Prior to Synopsys, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a PhD in Electronic Engineering from Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored multiple technical papers and presented in several technical conferences on analog and mixed signal design.     

Day Two: Wednesday, October 7


Virtual Prototyping for Automotive Software Development

9:30 a.m. - 11:00 a.m. CEST

This session features three presentations from industry experts highlighting various aspect of using Virtual Prototypes for Automotive Software development and testing. We cover the shift-left of Software bring-up for a next-generation AURIXTM MCU from Infineon the use of Virtual Prototypes for testing of safety critical automotive applications at Volkswagen the system design and Software development of Electric Vehicles. 

Wednesday, October 7 | 9:30 a.m. - 10:00 a.m. CEST

Software Development using Next Generation Infineon AURIX™ Virtual Prototypes

Description: This paper presents the usage and benefits of Virtual Prototyping (VP) for Embedded Software Development on the Infineon AURIX™ range of devices. The objective is to show the unique value of AURIX™ Virtual Prototypes for both pre and post silicon development and to give an insight into the long collaboration between Infineon and Synopsys in bringing differentiated Virtual Platforms to the market. The case study will examine safe and secure vehicle application development, from current to next generation. We will show how Infineon uses the Virtual Prototype internally to shift left software development and testing. We will also look at how continuous integration (CI) increases the efficiency of functional safety testing.  

Dineshkumar Selvaraj

Infineon Technologies AG

Speaker: Dinesh is currently leading the Virtual prototype development of AURIX family of Microcontrollers in Infineon Technologies. He has got 15+ years of experience in ESL domain with focus into development of VP for classical pre silicon SW validation, RTL co-simulation and also early performance analysis and optimization using models. Prior to Infineon, he worked with Intel and Tata Elxsi. He pursued electrical engineering from NIT, Trichy. 

Wednesday, October 7 | 10:00 a.m. - 10:30 a.m. CEST

Scaling Functional Safety Testing of Electronic Power Steering Systems with Virtualizer 

Description: Functional Safety (FuSa) is a key requirement of automotive systems. Especially highly available systems like Electronic Power Steering (EPS), where malfunctions can lead to life threating events, are governed by the highest Automotive Safety Integrity Level D (ASIL-D) as defined by ISO 26262.  In order to bring down the cost, the EPS development and test department at VW is shifting towards a virtual testing strategy using a virtual Hardware ECUs based on Synopsys Virtualizer. We leverage the fault injection capabilities to trigger safety critical fault conditions and thus increase the coverage of the control Software.  We are working on moving the software tests to a virtualized environment on a server farm, including state-of-the-art software engineering methods like continuous testing and continuous integration. In our presentation we will also share our experiences with the ASIL qualification process for ASIL D compliancy as well as mapping the original safety tests to the virtual Hardware ECU.  

Matthias Glück

Volkswagen AG

Speaker: Matthias is the technical lead for Testing Methodology and Strategy of Electric Power Steering systems at Volkswagen. He is also a member of the company-wide boards on test strategy and on virtual Hardware ECUs. Before joining Volkswagen in 2014, Matthias has worked for 11 years at Intel as a Senior Component Design Engineer in various testing and test methodology roles worldwide, e.g. for cyber security, hardware virtualization and supercomputing. Matthias holds a diploma degree in Electrical Engineering from Technical University Berlin. 

Wednesday, October 7 | 10:30 a.m. - 11:00 a.m. CEST

From System to Software: A Study in Efficient, Robust Design for Electric Vehicles

Description: In the fast-growing domain of electric vehicle development, many challenges exist. Range anxiety and cost are adoption barriers, in addition to challenges with hardware and software related to design complexity. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle as well as in the final product. This presentation discusses how a unified virtual prototyping solution, which addresses the multi-discipline needs of system, electro-mechanical, and embedded software domains, can help to “shift left” the design phase and accelerate testing efforts. The “shift left” practice enables finding defects early in the software development and testing process. 

The presentation includes a case study that looks at early verification requirements with fast, highly abstracted simulations, all the way through to highly refined simulations, and progresses through the design cycle. 

Topics covered include: 

A study of a high-level kilometer range, starting with the electromechanical system. An AUTOSAR application software simulation combined with a refined electromechanical plant simulation for accelerated development. Running a high-fidelity full software stack simulation with highly refined power electronics, serving as a foundation for full system verification.

Kevin Brand

Sr. Staff Applications Engineer, Verification Group, Synopsys

Speaker: Kevin is a Sr. Staff Applications Engineer at Synopsys. He has been in the field of virtual prototyping for 15 years. With a strong focus on automotive, he has been working in R&D and, in more recent years, directly enabling and deploying virtual prototyping solutions at semiconductor, Tier 1, and OEM companies.  

Robust Analog Mixed Signal Verification - Part 1

9:30 a.m. - 11:00 a.m. CEST

Automotive applications requires robust Analog designs so the reliability and safety becomes a must. This track will cover Synopsys reliability solution with a focus on TestMAX CustomFault as well as Synopsys Mixed-Signal verification providing the required performances for large circuits. 

Wednesday, October 7 | 9:30 a.m. - 10:30 a.m. CEST

Delivering Safe and Reliable AMS Designs with Synopsys TestMAX CustomFault

Description: The increased need for safety, low defect rate, and long-term reliability is driving automotive IC designers to augment expert judgement with fault simulation to analyze the impact of random hardware defects on design safety and reliability and ensure compliance with ISO 26262 requirements. This tutorial provides an overview of how Synopsys TestMAX CustomFault can be used to accelerate block-/IP-level functional safety and test coverage, and enable SoC-level FMEDA analysis in conjunction with Synopsys Unified Functional Safety solution.  

Anand Thiruvengadam

Senior Manager, Design Group, Synopsys

Speaker: Anand Thiruvengadam, a Senior Manager in the Design Group at Synopsys, is responsible for circuit simulation product marketing. Anand has 15+ years of combined experience in high technology product management and product development. Prior to Synopsys, he worked at PriceWaterhouseCoopers (PwC) as a management consultant, focusing on strategic and operational transformation initiatives for various enterprises in the consumer electronics, networking, storage, enterprise software, and semiconductor industries. Prior to PwC, Anand worked at AMD and Alliance Semiconductor, where he successfully led the design and development of high performance Analog, PMIC, and Memory products. Anand has an M.B.A. from the Haas School of Business at University of California, Berkeley, and an M.S in Electrical Engineering from Oklahoma State University.

Wednesday, October 7 | 10:30 a.m. - 10:45 a.m. CEST

Analog Fault Simulation in ISO26262 Applications

Description: In our presentation, we will talk about application areas for analog fault simulation, it's challenges and compare a few different approaches used in the commercially available tools. We explain how we apply CustomFault to determine ISO 26262 metrics required as input to FMEDA, the challenges this presents, and how we partnered with Synopsys to resolve these challenges. We close with a few illustrating examples. 

Gernot Koch

CAD Manager, TDK-Micronas GmbH

Speaker: Gernot Koch holds a Master in Computer Science from Karlsruhe Institute of Technology (KIT) 1993 and a Doctorate in Computer Science from University of Tübingen, 1998. He spent 5 years developing EDA tools in California (Synopsys, Bridges2Silicon). He "Switched sides" in 2003, and became a CAD engineer at Micronas (now TDK-Micronas), specializing in System Level Design, analog and digital verification, and PDKs. Managing CAD team at TDK-Micronas since 2009.  

Wednesday, October 7 | 10:45 a.m. - 11:00 a.m. CEST

TestMax CustomFault for failure analysis of Analog mixed signal IP’s

Description: The increasing complexity of the circuits due to the constant integration of new technologies presents new challenges for manufacturing test methodologies and analysis. This is especially true in some critical field like automotive due to the safety application requiring an efficient failure analysis in order to find a corrective action and evaluate the risk for a population with failure. This presentation will deal with the integration of the analog simulation in the normal failure analysis flow. In particular, we will show how the results can be used as key step for the fault isolation speeding up the whole analysis process. Starting from this new flow we will also show how CustomFault  in our process is shortening the identification of failure through examples of failure analysis.

Tommaso Melis

STMicroelectronics

Speaker: Tommaso Melis got a Master of Science degree in Electronic Engineering in the University of Cagliari, Italy. He started his activity as a trainee student inside STMicroelectronics in 2017 in the Automotive Discrete Group working in the failure analysis team. Inside the same team in the 2018 he started a PhD with the TIMA Laboratory and STMicroelectronics in Grenoble. His work is now focused on the development of automatic tools for the failure analysis in analog and mixed-signal circuits.  

Automotive IP for ADAS Applications

9:30 a.m. - 10:30 a.m. CEST

Learn about IP requirements for safety-critical ADAS applications including AEC Q100 reliability testing, ISO 26262 compliant development process to achieve ASIL targets, and ISO 9001 automotive quality management system.

Wednesday, October 7 | 9:30 a.m. - 10:30 a.m. CEST

Automotive IP Supporting ASIL D Systematic for ADAS Applications

Description: This session describes automotive IP for safety critical ADAS applications.  The IP must meet requirements for ASIL target safety integrity levels including compliance to ASIL systematic development flow. Both the safety critical ADAS SoC and IP must go through comprehensive steps to meet automotive-grade standards including ISO 26262 functional safety, AEC Q100 reliability, and ISO 9001 quality management system. Learn more about the automotive IP including ISO 26262 compliant development process to achieve ASIL systematic targets.

Ron DiGiuseppe

Sr. Strategic Marketing Manager, Solutions Group, Synopsys

Speaker: Ron DiGiuseppe, Senior Strategic Marketing Manager at Synopsys, is responsible for automotive segment marketing for Synopsys DesignWare IP solutions for ADAS, Functional Safety, Infotainment and MCU applications. Ron brings more than 18 years of semiconductor experience to Synopsys. Prior to joining Synopsys, Ron held a range of management positions at Xilinx for automotive connectivity IP products as well as engineering development and management roles for companies including Oki Semiconductor, NEC, and Raytheon Corporation. Ron DiGiuseppe holds a bachelor's degree in Electrical Engineering from San Jose State University and a Certificate in Network Engineering from University of California.

Synopsys Verification Continuum Platform

11:15 a.m. - 12:45 p.m. CEST

In this session, we will cover software and hardware based verification technologies tackling SoC verification challenges. Verify the entire SoC with industry-leading VCS® simulation, Verdi® debug, VC SpyGlass™ and VC LP™ for RTL signoff, VC Formal™ to catch bugs early, and silicon-proven Verification IP. Leverage ZeBu®, the industry’s fastest emulation solution for early software bring-up and validate the entire system with Virtualizer™ virtual prototyping and HAPS® prototyping solution.

Wednesday, October 7 | 11:15 a.m. - 12:45 p.m. CEST

Synopsys Verification Continuum – Finding the Tough Bugs in your Hardware and Software 

Description: As SoC designs evolve and grow in complexity, so do the testbenches and verification flows built around these designs. Given the sheer volume of complex protocols, increased software content, architecture complexity, and need for low power; identifying which verification technology is the best fit for your project is essential. This session will walk through each of the mentioned challenges and how designers are leveraging the Synopsys Verification Continuum® platform to find SoC bugs earlier and faster, bring-up software earlier, and validate their entire system.  

Topics covered include: 

Integrated Development Environment (IDE) for correct-by-construction RTL/Testbench 

Low power analysis and verification  

Comprehensive mixed signal solution 

Use of machine learning technology to improve coverage, performance, and debug  

Methodology to transition from IP to SoC verification 

Software bring-up pre-silicon  

Pre-silicon system validation using emulation and prototyping  

 

Yassine Eben Aimine

Applications Engineer, Verification Group, Synopsys

Speaker: Yassine is a Verification Applications Engineer at Synopsys in the UK. Yassine has worked on several parts of the IC design and verification flow, ranging from synthesis, ATPG to functional verification. Yassine is currently Synopsys’ functional and FuSa verification expert for digital IPs and SoCs and provides technical guidance and support to Synopsys customers in Europe. Yassine holds a Master’s degree in microelectronics from the Ecole Nationale d’Electronique de Toulouse. 

Fabian Delguste

Applications Engineer, Verification Group, Synopsys

Speaker: Fabian has been in the industry for 20+ years. He has expertise in SW development, HW design and EDA. He is in charge of a team of AEs in Europe. His charter is to deploy emulation and prototyping solutions to key accounts in Europe. Fabian holds a MSEE and graduated from “École Polytechnique de l'Université de Nantes”. 

Robust Analog Mixed Signal Verification - Part 2

11:15 a.m. - 12:35 p.m. CEST

Automotive applications requires robust Analog designs so the reliability and safety becomes a must. This track will cover Synopsys reliability solution with a focus on TestMAX CustomFault  as well as Synopsys Mixed-Signal verification providing the required performances for large circuits. 

Wednesday, October 7 | 11:15 a.m. - 12:15 p.m. CEST

Mixed Signal Verification—How Designers use Synopsys’s Mixed-Signal Solution to Develop Intelligent Testbenches, Improve Simulation Performance and Analog Test Coverage

Description: The Mixed-Signal Verification solution from Synopsys offers a variety of features and techniques to develop smart testbenches that check the behavior of both the analog and digital parts of a design, and provides capabilities to significantly shorten the simulation run times and improve test coverage. In this session we review some of the key features in Synopsys’s Mixed-Signal solution that allow those capabilities.

 

Farzin Rasteh

Sr Mgr. Applications Engineer, Design Group, Synopsys

Speaker: Farzin Rasteh is the senior Application Engineering Manager for Analog and Mixed-Signal Verification at Synopsys. He is an Electrical Engineer with experience in signal integrity, RF, and analog IC design, as well as ASIC design and verification, and emulation. For more than 10 years Farzin has been managing the support and methodology development for Analog and Mixed-Signal verification tools at Synopsys . Farzin has a Bachelor’s degree in Electrical Engineering from Sharif University of Technology in Iran, and Master’s degree in Information Technology from Carleton University, Canada.

Wednesday, October 7 | 12:15 p.m. - 12:35 p.m. CEST

eSTM Flash Memory IP AMS Verification Strategy & Device Modelling Improvements

Description: Flash memory IP is a complex block which contains both digital and analog parts, such as charge pumps and oscillators. Because of their relatively high operating frequency (can be above 100 MHz), they represent a huge cost in terms of simulation time, particularly for the erase operation. We propose a mixed mode simulation approach, based on XA-VCS to validate the Flash memory IP in a reasonable time with good level of precision. Flash bitcell modelling has been optimized, giving rise to huge runtime improvement.

 

Thomas Jouanneau

PHD, NVM Analog & Mixed Design, STMicroelectronics

Speaker: Thomas Jouanneau graduated from Grenoble INP in microelectronics engineering. After a PhD in process technology in the CEA-Leti, he was hired in STMicroelectronics Grenoble as digital back-end designer in 2012. He worked on digital SoC aimed for mobile phones or set-top-box. Since 2016, he moved to analog design for non-volatile memories in the Microcontroller & Digital Group. He is now focused on analog design, and full chip verification with Analog-Mixed-Signal simulation tools. He was recently appointed as Mixed-verification leader.

High-Performance Real-Time Processors for Embedded Applications

11:15 a.m. - 12:15 p.m. CEST

Performance requirements for high-end embedded applications are increasing but there are limits on power and area in embedded applications that must be accounted for. This is driving the increasing use of configurable multicore solutions and specialized hardware accelerators to deliver the required performance. Learn how a multiprocessor cluster architecture that is highly scalable to achieve very high performance for a range of high-end embedded applications.

Wednesday, October 7 | 11:15 a.m. - 12:15 p.m. CEST

How to Get from Here to There in Real Time: The Future of High Performance Embedded Processing

Description: The requirements for embedded processing are changing as high-performance infrastructure spreads from the cloud to end points of the internet. The capabilities and functionality of these processors are especially fundamental to the implementation and operation of real-time applications.  For all embedded applications (including real-time), power and area constraints restrict what can be done to increase processor performance, driving the use of configurable multicore solutions and specialized hardware accelerators in next generation embedded architectures. This presentation will look at the future structure of embedded processors that deliver the performance, scalability and flexibility needed to address the ever-increasing real-time performance requirements for storage, automotive, networking, mobile and other high-end embedded applications.  

 

Paul Stravers

Principal R&D Engineer, Solutions Group, Synopsys

Speaker: Paul Stravers is an ARC computer architect with Synopsys since 2016, working on next generation processors and memory subsystems. Before joining Synopsys Paul has held industrial positions in the field of computer architecture, multicore application mapping, hardware-software codesign,  semi-automatic  parallelization and tools to improve software integrity.