Synopsys Technology Symposium France 2018

Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share.

Multiple tracks will be offered including Implementation, Verification, Test and Custom/AMS where experts will update you on exciting new technologies and features.

We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere. Stay with us for refreshments and a chance to win nice prizes.

Date and Venue

Thursday, 27th September
World Trade Center, 5-7, Place Robert Schuman, 38000 GRENOBLE
9:00 a.m. - 6:00 p.m.

Registration starts at 9:00 a.m. The technical program will kick off at 10:00 a.m. with a keynote by Dr. Antun Domic, Chief Technology Officer, Synopsys, Inc.  To register click on the links below or visit:

09:00 - 10:00

Registration and Light Breakfast - Atrium

10:00 - 11:00

Welcome and Keynote
"Thinking Outside the CMOS Box"
Dr. Antun Domic, Chief Technology Officer, Synopsys, Inc.


11:00 - 11:15

BREAK - Atrium


Mont-Blanc 1

Kilimandjaro 1

Kilimandjaro 3

Mont-Blanc 4

11:15 - 12:15

A1 - RTL to GDS

A2 - Functional Safety

A3 - Test Flow for Automotive SoC

A4 - VCS AMS Advanced Flow

Runtime-Tuning for Design Compiler - Synopsys

Functional Safety for Today's Complex SoCs - Synopsys

Synopsys Test Solution Flow for Automotive -Synopsys

Modeling an Auto-connecting Leaking Capacitor on a SV-nettype Power Supply in VCS AMS - STMicroelectronics

PageFlash Memory Verification: AMS Strategy and First Results - STMicroelectronics

Achieving Out-of-the-Box Results with IC Compiler II - Synopsys

VCS AMS UPF - STMicroelectronics

12:15 - 13:30

LUNCH - Atrium

13:30 - 15:00

B1 - Synopsys Fusion Technology

B2 - Static and Dynamic Verification Update

B3 - DFT for Complex Hierarchical SoC

B4 - Advanced Flow and CustomSim Update

Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology - Synopsys

Clock & Reset Domain Crossing (CDC/RDC) Verification Update - Synopsys
+ Multi Modal CDC Structural Checks Flow - STMicroelectronics

A Case Study of Test Point Insertion for Improving Testability - Infineon & Synopsys

New Methodology for Accurate Modeling of BCD High Voltage Poly Resistors Based on Quickcap and StarRC - STMicroelectronics

Memory Test & Repair and Hierarchical Test of Interface IP - Synopsys

 CustomSim 2018.09 Update - Synopsys

Update VCS / Verdi - Synopsys

ECO Fusion Delivering Best QoR and Fastest Time to Results - STMicroelectronics

15:00 - 15:30

BREAK - Atrium

15:30 - 17:00

C1 - Machine Learning

C2 - HW and Formal Verification

C3 - ATPG, Diagnostic and Yield

C4 - Analog Custom Implementation

Bringing Digital Intelligence to the Synopsys Design Platform - Synopsys

Billion Cycle Power Estimation with Zebu - Synopsys

Is the Default TetraMAX Transition Fault List Adequate? - Dialog Semiconductor

Creating Common Centroid Layout with Custom Compiler - TDK-Micronas GmbH

Successful Chain Diagnosis in Complex SoC - STMicroelectronics

CustomCompiler 2018.09 Update - Synopsys

VC Formal Update: New Apps for Security, X propagation, Regression Acceleration and Formal Testbench Analysis - Synopsys

Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning - Synopsys

Yield Explorer Update - Synopsys

17:00 - 18:00

Networking and Refreshments

Keynote and Joint Abstracts

Keynote: Thinking Outside the CMOS Box

Even if the progression of Moore’s law continues relentlessly, in 2040 it would still take the world fastest supercomputer a billion years to factor RSA-2048, a 617-digit semiprime number, and the simulation of nitrogenase enzyme co-factor, a fairly simple organic molecule, would not be completed before the end of our universe.
Lagging microprocessor frequency, latency across the processor, memory, and storage stack, as well as the signal losses in electrical transmission lines prevent breakthrough improvements in performance and power efficiency.
The computing and memory requirements of artificial intelligence (AI), biochemistry, medicine, pharmacology, and physics applications greatly exceed the capabilities of current electronics and are unlikely to be met by isolated improvements in devices, or integrated circuit architectures alone.
Circuits based on super-conducting electronics (SCE) have made many advances in the last few years. Short term, Josephson junction-based SCE promises to invigorate HPC by delivering at least an order of magnitude more performance using 100X less power. Longer term, SCE is the best available foundation for a new class of computers, based on the laws of quantum physics, quantum computers (QC), which may dramatically change the landscape of HPC for problems that can be handled by this class of very different hardware.
Exascale computing demands for exascale bandwidth: silicon photonics is capable of dramatically faster data communications, at a much lower power, and can play a critical role as a link between the sub-4°K SCE/QC world and the room temperature (300°K), classical computing world.
Discrete and monolithic 3D-IC may help unleashing the full potential of heterogeneous integration of different functions – compute, store, sense/actuate – and could allow for their independent evolution, both w.r.t. the process technology and the design tools.
This talk offers an overview of the looming innovations that may change the landscape of our industry.


Runtime-Tuning for Design Compiler

Growing design complexity and new emerging nodes introduce new challenges during synthesis and optimization. This Session will focus particularly on the advancements in the Design Compiler family to address runtime challenges.

Achieving Out-of-the-Box Results with IC Compiler II

This tutorial provides an update on the latest design implementation technologies available in the IC Compiler II 2017.09 and SP releases to achieve improved out-of-the-box QoR. Attend this session to learn how to deploy these latest technological advancements in your physical implementation flow.

Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology

Learn about the latest developments on the Synopsys Design Platform to improve QoR for your advanced designs. Learn also about the breakthrough Fusion Technology that transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools. Fusion Technology enables you to accelerate the delivery of your designs with the industry-best full-flow QoR and the fastest time-to-results.

ECO Fusion Delivering Best QoR and Fastest Time to Results

This presentation will provide an insight into some of the innovative Synopsys platform technologies that enable STMicroelectronics to achieve best QoR and fastest TAT on their designs. We will share our experience on how we successfully utilized ECO Fusion technology from Synopsys to close our design in IC Compiler II.

Bringing Digital Intelligence to the Synopsys Design Platform

Machine learning (ML) is emerging as a powerful technology for addressing high-complexity, high-cost challenges across a multitude of applications in chip design. This presentation will discuss Synopsys approach to ML and illustrate examples of how this new, digital intelligence is making it possible to accelerate design turnaround and achieve optimal quality-of-results.

Signoff Power Analysis Driven PrimeTime ECO for Best PPA - Accelerated by Machine Learning

In this tutorial, we will review the signoff power-driven timing and power closure features in PrimeTime® ECO. Driven by PrimeTime PX signoff power analysis, PrimeTime physically-aware ECO can deliver the best dynamic, leakage, and total power Quality of Results (QoR) while achieving signoff timing closure. We will also provide a preview of machine learning technology that can deliver the same superior QoR with 5X faster TAT. This tutorial is for all current and upcoming PrimeTime ECO users.


Functional Safety for Today’s Complex SoCs

Application of ISO 26262 to complex devices presents unprecedented challenges for functional safety tools. State-of-the-art SoCs targeting autonomous driving consist of a wide variety of proprietary and 3rd party IPs. The failure mode analysis of these 100+ units is distributed to many engineers with domain expertise. These analyses must then be combined to create a coherent device-level FMEDA. In this session we will discuss the challenges associated with a complex SoC FMEA/FMEDA requirements and the need for automation in the functional safety verification flow. We will highlight how Synopsys functional safety verification solution including technologies for FMEDA automation and fast fault injection enables IP and Semiconductor companies to scale their development activities for complex designs requiring many simultaneous users across the SoC development and verification teams.

Clock & Reset Domain Crossing (CDC/RDC) Verification Update


Multi Modal CDC Structural Checks Flow

Clock Domain Crossings (CDCs) and Reset Domain Crossings (RDCs) have the same devastating consequences causing functional failures due to un-managed metastability, clock ratio and convergence. CDCs and RDCs are a leading cause of chip failure with growing design complexity and multiple power domains. This session covers an introduction on the failure causes and an update on our leading Static Verification solution for CDC and RDC.

On top of that, STMicroelectronics will share their experience and present a way to accelerate the CDC Structural Checks task in the context of a multi-CPU 64 bits Sub-System using SpyGlass in a Multi-Modal approach.

Update VCS / Verdi

Complex designs require sophisticated verification techniques in order to reduce simulation time and increase debug efficiency.

This presentation will go through the Synopsys Verification Solution and will provide an update on the latest verification technologies introduced in VCS and Verdi 2018.09.

In this tutorial, we will cover the following technologies: Xprop, C Testbench debug, Fine Grain parallelism, Constraint Debug, Simulation profiling, Reverse Debug, Automated Root Cause analysis and more…

Billion Cycle Power Estimation with Zebu

Power analysis with simulation has always been limited by number of cycles that can be run in a reasonable amount of time. This prevented realistic embedded software tests from power estimation flows. With ZeBu power estimation, this is no longer the case - billions of cycles can be run and analyzed for average and peak power with high accuracy.
This session will give an overview of the advantages of ZeBu power estimation compared to traditional techniques.

VC Formal Update: New Apps for Security, X propagation, Regression Acceleration and Formal Testbench Analysis

This section covers the latest enhancements and Apps that are now complementing VC Formal.

Formal Security Verification (FSV) and Formal X-propagation (FXP) have recently been added to the VC Formal portfolio.

Regression Mode Acceleration (RMA) is a machine learning algorithm that help to drastically reduce the convergence time of formal verification.

FTA app (Formal Testbench Analyzer) results of the integration of Certitude’s fault injection in VC Formal.


Synopsys Test Solution Flow for Automotive

Automotive products are required to fulfill the highest quality levels. Safety Critical parts require adherence to ISO26262 and ASIL (A, B, C, or D) according to the targeted application scenario. The presentation will show how the Automotive Logic BIST methodology, flow, and implementation will satisfy the functional safety requirements as well the manufacturing quality.

A Case Study of Test Point Insertion for Improving Testability

Test Point Insertion (TPI) is an effective method for improving DFT measures without compromising the schedule of a project. There are mainly three different purposes: (i) increase of ATPG performance in order to yield a higher deterministic Test Coverage (TC), (ii) reduction of scan volume and (iii) improvement of random testability, i.e. increase of TC for a certain number of Logic BIST cycles. Often the TPI results aiming for one specific goal show a smaller effectivity for any alternative or additional goal. The Synopsys TPI technique is able to determine test points that are well suited for several purposes simultaneously. This paper presents a case study of Synopsys TPI approach applied to a set of Automotive Designs of Infineon. It will be shown that the provided TPI method is able to increase the TC for ATPG while reducing the overall pattern count simultaneously. Also pseudo random pattern TC as required for LBIST can be improved while requiring fewer test patterns.

Memory Test & Repair and Hierarchical Test of Interface IP

Today's IC designers need the functionality offered by different types of memories: single/two/dual/multi-port/ROM/high performance CPU cache, while accounting for new and increased memory fault types due to 3D transistor structures. On the other hand, complex interface IP, like DDR, USB, PCI-E, require observability and controllability from a test and efficient scheduling stand point. Finally, market specific requirements, like automotive, mandate compliance to stringent functional safety standards and high reliability in terms of flexible in-field test capabilities to ensure low defective parts per million (DPPM). This tutorial will discuss the DesignWare® STAR Memory System (SMS), Synopsys memory test and repair solution, as well as the DesignWare STAR Hierarchical System (SHS), the hierarchical test and diagnostics solution for all IP/cores on your SoC, including interface IP, analog/mixed signal IP and digital logic blocks. The tutorial will cover the design flow, manufacturing test and repair, and in-field self-test and reliability strategies, capabilities and use models.

Is the Default TetraMAX Transition Fault List Adequate?

For stuck-at faults the default fault list, created using add_faults all, contains stuck-at fault on all potential fault sites. Typically, these would be the pins of standard cells in the design library. However, for transition faults, the faults classified as clock are excluded from the default fault list. In some recent designs the resulting transition fault list is less than half the size of the stuck-at fault list. This paper examines the reasons why these faults are classified as being of type clock and describes techniques for analyzing them. It can be shown that typically about 80% of these excluded faults can be tested.

Successful Chain Diagnosis in Complex SoC

This presentation will share STMicroelectronics experience on identifying yield detractor on complex SoC, specifically focusing on Chain Defects and how to improve the accuracy and precision in presence of multiple defective chains. The presentation would provide methodological indications as well practical example on how to optimize the Test Program, generate Chain Diagnostic specific patterns, and actual successful examples of the application of such methodology.

Yield Explorer Update

Understanding root cause mechanisms that can affect IC yield and product reliability is important when targeting deep submicron ASIC technologies. This presentation update will show latest available features of Yield Explorer Volume Diagnosis analysis solution (YE), showing the different analysis tools available, such as DART (Diagnostic Analysis Readiness Tool), AVD (Automated Volume Diagnostics), FMA (Failure Mechanism Analysis), and FAST (Failure Analysis Selection Tool) with Avalon direct link for Failure Analysis automation, to help customers and foundries understand the root causes of yield loss, such as design or process related, and improve design and process towards higher Yield.


Modeling an Auto-connecting Leaking Capacitor on a SV-nettype Power Supply in VCS AMS

SystemVerilog nettypes are mainly used to emulate Verilog-AMS wreal, implement Ohm’s law for one terminal, or interact with UPF signals.
We propose here an extension of wreal usage, in order to facilitate debug of average resolution function, as well as implementation of extra features such as an auto-connecting model of leaking capacitance. On top of implementation with VCS, the challenges of CustomSim-VCS simulations for this kind of custom structure at analog boundary are discussed.

PageFlash Memory Verification: AMS Strategy and First Results

Flash memory IP is a complex block which contains both digital and analog parts, such as charge pumps and oscillators. Because of their relatively high operating frequency (can be above 100 MHz), they represent a huge cost in terms of simulation time. We propose a mixed mode simulation approach, based on XA-VCS to validate the Flash memory IP in a reasonable time with good level of precision. Different modelling strategies are described: historical with spice and optimization with SystemVerilog. First simulation results are presented and discussed.


Integrating Analog designs, especially Power Management Unit becomes more and more critical in SoC digital designs. In order to increase our analog verification coverage, we introduced Analog/Mixed-Signals simulations few years ago in a complex flow which was time-consuming to setup, fine-tune and maintain. As another step towards higher efficiency, we would like to benefit from UPF IEEE-1801 standard to integrate Spice views into our existing low-power verification flow. AMS emerges as the 3rd layer on top of UPF and RTL simulation sheets.

New Methodology for Accurate Modeling of BCD High Voltage Poly Resistors Based on QuickCap and StarRC

High voltage technologies are important in many areas of IC design like automotive; some high voltage devices are critical from modeling perspective and need specific attention in the overall design flow.

In detail, high voltage poly resistors cannot be managed as standard for their particular circular shape; the usual spice model is not enough accurate because it doesn’t take into account all possible layout configurations.

The aim of this article is to show the methodology developed in collaboration between STMicroelectronics and Synopsys to correctly model Poly Resistors in design flow.

The first part shows how the QuickCap Field Solver flow is customized to generate a complete distributed “layout configuration-based” RC network.

The second part shows how the QuickCap flow is integrated in the StarRC flow generating a unique generic parasitic netlist to be simulated.

CustomSim 2018.09 Update

The CustomSim O-2018.09 release is a major release that includes new features and bug fixes. The presentation will highlight the solution Synopsys can offer for more robust designs. New features, like the Measure Analyzer, the version 2 of set_sim_level command, how to dynamically change the tolerance and all 2018.09 new features will be presented.

Creating Common Centroid Layout with Custom Compiler

Creating good matching layout for precise implementations of current mirrors or other structures is a challenge. Since Custom Compiler features Symbolic Editor, it has the bare basics necessary for manipulating such layouts, but it does not offer any automation in creating good device placement. Therefore, we have created a custom application to automate placement which integrates with Custom Compiler and Symbolic Editor. Our contribution describes the requirements, challenges and use models of this application, and how it integrates into Custom Compiler.

Custom Compiler 2018.09 Update

Please check back later for details