Synopsys Technology Symposium 2019

Synopsys Northern Europe is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at emerging and established nodes.

This event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that our experts will share.

Synopsys technical experts will provide an “under the hood” look at proven and new technologies that designers can use to meet their aggressive time schedules and to achieve challenging Performance, Power and Area goals.

Multiple tracks will be offered where experts will update you on exciting new technologies and features that are now available. 

We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere. You will also have the opportunity to win one of our prizes in our Prize draw at the end of the day.

Garmin Forerunner 735XT GPS Multisport and Running Watch

Garmin Forerunner 735XT GPS Multisport and Running Watch

Sony WH-CH700N Wireless Bluetooth Noise Cancelling Headphones

Sony WH-CH700N Wireless Bluetooth Noise Cancelling Headphones

AKASO EK7000 4K Sport Action Camera Ultra HD

AKASO EK7000 4K Sport Action Camera Ultra HD 

Thursday, 14th November
Hilton Reading, Drake Way, Reading, RG2 0GQ UK

If interested, you are welcome to move between tracks. The tracks commence at 9:30am with registration and refreshments from 8.30am. To register click on the links below.

http://events.synopsys.com.

Venue

Hilton Reading, Drake Way, Reading, RG2 0GQ UK

There are limited rooms available at the Hilton for the night prior to the event at a discounted rate. Please click here to book.

Detailed Agenda

0830 - 0930
Registration and Breakfast
Windsor Foyer
Track Front End Implementation Track Place & Route Implementation Track Test Solutions and Automotive Verification Track
0930 - 1230 RTL Synthesis 2019.03+ Update and Roadmap Fusion Compiler 19.03 Update and Roadmap Synopsys TestMAX: Redefining Expectations for Test Automotive Functional Safety
New Features for Automotive Functional Safety in
Synopsys’ RTL-to-GDSII Flow
Formal to the rescue for Safety and Security Applications
Formality and Formality ECO update
Joint Implementation Track
Cloud Scale EDA
1230 - 1400
Lunch Service
Keynote Address: Michael Sanie, Vice President Product Marketing, Design Group, Synopsys Inc. - Windsor 1
Lunch Service
Track Front End Implementation Track Place & Route Implementation Track   VG
1400 - 1630 PrimeTime 19.03 Update and Roadmap ICCII Place and Route 19.03 Update and Roadmap   What's New in VCS and Verdi
 
 
  Machine Learning Cutting Debug Time by 10x For Low Power and CDC Analysis
Galaxy Low Power (UPF) 19.03 update Physical Signoff 19.03 Update and Roadmap  
 
  The State of the Play with HAPS Based FPGA Prototyping
ECO Fusion and Roadmap
 
 
 
1630 - 1730
Social

General

Cloud Scale EDA Abstract: In this session we will explore how Synopsys is preparing for and enabling the next generation of silicon design in cloud environments.

DG, Front End

Cloud Scale EDA Abstract: In this session we will explore how Synopsys is preparing for and enabling the next generation of silicon design in cloud environments.
RTL Synthesis 2019.03+ Update and Roadmap Abstract: In this section we will introduce our next generation synthesis offering,  Design Compiler NXT and provide updates for all the DC suite of tools. These enhancements will cover, improve correlation to back-end, quicker time to results (TTR) , improves power, performance and area (PPA), enhanced language support
Formality and Formality ECO 2019.03 Update and Roadmap Abstract: In this section we will introduce our new Automatic ECO capabilities, review the interactive ECO features and provide updates for the 2019.03 release of Formality. This will included enhances to enable improved completion, additional debugging capabilities for both failing and hard verifications. 
Galaxy Low Power (UPF) 19.03 Update Abstract: In this session we will cover the 19.03 enhancements to the Galaxy Low Power Platform. This will include enhancements to IEEE1801 construct support, UPF implementation support and usability improvements.
PrimeTime 19.03 Update and Roadmap Abstract: This session will introduce new features of the PrimeTime 2019.03 release including full flow performance improvements, enhanced ECO
techniques including simultaneous fixing techniques, TNS reduction, crosstalk minimization, and interactive physical ECO enhancements.
We will also introduce the newly announced PrimeYield product which is the industries fastest robustness, high-sigma and statistical yield
analysis and optimization solution. In addition we will highlight some exciting technologies from the Synopsys signoff roadmap.

DG, Joint Front End and Back End

ECO Fusion 19.03 Update & Roadmap Abstract: This session will contrast ECO Fusion with PT-ECO illustrating the fundamental usage models and the added value  of ECO Fusion. It  will discuss the latest features before moving on to examining recommendations for best practice.
Case studies will be used to reinforce best practices and provide usage & debug tips to ECO Fusion users.
The presentation will conclude with a roadmap of upcoming features.

DG, Back End

Fusion Compiler 19.03 Update and Roadmap Abstract: In November 2018 Synopsys announced Fusion Compiler. Fusion Compiler is the only complete RTL to GDS tool, which enables it to deliver leading QoR and significant productivity improvements. In this session we will provide an overview of what makes Fusion Compiler unique followed by a deep dive into the core technologies
ICCII Place and Route 19.03 Update and Roadmap Abstract: 2019.03 IC Compiler II update
This session will review the latest features available in the IC Compiler II 2019.03 product update including related service packs.  The main topic areas covered:
• Power/Performance/Area (PPA) and Runtime Improvements
• Advanced technology node support
• Fusion technologies
 
We'll discuss a wide range of topics throughout the Place & Route flow and highlight how these latest technologies can assist the variety of goals typically faced by Physical Designer engineers.
Physical Signoff 19.03 Update and Roadmap Abstract: This session will provide and update of the latest IC Validator enhancements and will outline how productivity can be improved. Enhancements have also been made to the StarRC family and these will also be discussed

Test

Synopsys TestMAX: Redefining Expectations for Test Abstract: The Synopsys TestMAX™ family of products offers innovative, next-level test and diagnosis capabilities for all digital, memory and analog
portions of a semiconductor device. This session will give an introduction to the new comprehensive test automation solution spanning from
early RTL validation right through to in-system test and diagnosis, integrated within the Synopsys Fusion Design Platform.
New Features for Automotive Functional Safety in
Synopsys’ RTL-to-GDSII Flow
Abstract: Automotive Integrated Circuit (IC) designers use Triple Mode Redundancy (TMR) and Dual Core Lock Step (DCLS) redundancy strategies as safety mechanisms to mitigate the effects of random hardware failure to ensure functional safety for the different ISO 26262 safety integrity levels of designs. Synopsys has introduced new native capabilities in its RTL-to-GDSII tool flow to allow designers to easily place, verify, visualize and report implementation of redundancy. In addition to this, Synopsys now provides a static analysis solution to identify where the safety mechanisms are needed and also what effect these structures will have on the safety integrity of the design. With deployment of these new features, designers can achieve better Ease-of-Use (EoU) and Quality-of-Results (QoR) from their automotive design flows. This presentation will describe the new features in the context of a full digital implementation flow as demonstrated on a sample design.
Automotive Functional Safety Abstract: What is functional safety? How is it done? What is different in functional safety verification from what we have done for the last several decades? Will you be able to relax and feel safe in autonomously driven cars?

VG

Formal to the rescue for Safety and Security Applications Abstract: Mission critical systems need reliable software to tell you how your product will operate in the event of a crisis. VC Formal FUSA from Synopsys can stress test your designs by instrumenting faults in RTL and check if they propagate, if they are detected and if your design has managed to mitigate them. Make your designs functionally safe using Synopsys VC Formal.
What's New in VCS and Verdi Abstract: An update on the new features and functionality present in the tool's latest releases
Machine Learning RCA Cutting Debug Time by 10X For Low Power and CDC Analysis Abstract: NexGen SoCs with advanced graphics, computing and Artificial intelligence capabilities are posing new unseen challenges in verification. Designers and verification engineers using static verification technologies like LP/CDC/RDC often complain about the large number of violations generated by these tools. Efficiently debugging and root-causing issues becomes a huge challenge. This tutorial will talk about the present application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for related group of violations. This will significantly help to reduce the overall TAT for verification closure ensuring a “shift-left” and also make sure that subtle bugs do not escape into silicon
The State of the Play with HAPS Based FPGA Prototyping Abstract: With FPGA Based prototyping now an established Software Development and System Validation technology, the most recent focus has been on extending visibility techniques to enable more effective debug capabilities. This session will overview those latest techniques and some of the innovative ways they have been deployed to enable further adoption.