Synopsys Technology Symposium 2018

Synopsys Northern Europe is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest Implementation, Custom/AMS and Verification innovations as well as getting tips & tricks and best practices that our experts will share.

Multiple tracks will be offered including Implementation, Verification and Custom/AMS where experts will update you on exciting new technologies and features that are now available.

We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere. You will also have the opportunity to win an Amazon Echo Plus, Amazon Echo Spot or an Amazon Echo Dot in the prize draw at the end of the day.

Tuesday, 25th September
Hilton Reading, Drake Way, Reading, RG2 0GQ UK

If interested, you are welcome to move between tracks. The tracks commence at 09.30 a.m. with registration and refreshments from 8.30 a.m. To register click on the links above or visit:


Hilton Reading, Drake Way, Reading, RG2 0GQ UK

There are limited rooms available at the Hilton for the night prior to the event at a discounted rate. Please click here to book.

Detailed Agenda

0830-0930 Registration and Breakfast - Windsor Foyer

Front End Implementation 
Track (Windsor 1)
Place & Route Implementation 
Track (Windsor 2)
Functional Verification 
Custom and AMS 
0930-1230 Synthesis, Low Power & FV 18.06 Update and Roadmap Place and Route 18.06 Update and Roadmap Formal Techniques Large scale Monte Carlo analysis and data mining
SpyGlass Update Delivering robust AMS designs - fault simulation for analog
ICV 18.06 Update & Roadmap Verdi-VCS 2018.09 Update Custom Compiler, in-design EM analysis and Parasitic estimation
Joint Implementation Track (Windsor 1)
Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology
Dr Thomas Andersen, Synopsys Inc.
ZOIX Custom Compiler template-based design for layout assistance
1230-1400 Lunch Service - Windsor Foyer / Windsor 1
Keynote (Windsor 1). Dr. Antun Domic, CTO, Synopsys Inc.
Lunch Service - Windsor Foyer / Windsor 1

Joint Implementation Track (Windsor 1) Test Solutions and Automotive (Wilde) Custom and AMS (Foundry)
1400-1630 Bringing Digital Intelligence to the Synopsys Design Platform
Dr Thomas Andersen, Synopsys Inc.
SpyGlass DFT ADV Utilizing VCS AMS for high performance mixed Signal Verification
Cell Aware Testing and Yield Analysis Analog debug - Custom WaveView Update
Front End Implementation Track (Windsor 1) Place & Route Implementation Track (Windsor 2)
PrimePower RedHawk Fusion
Functional Safety and DFT Advanced electrical rule checking - Circuit check overview and update
PrimeTime 18.06 Update and Roadmap ICCII Design Planning
1630-1730 Social and Prize Draw - Windsor Foyer

Keynote and Joint Abstracts

Achieving Best QoR and Fastest TAT with Synopsys Fusion Technology

Learn about the latest developments on the Synopsys Design Platform to improve QoR for your advanced designs. Learn also about the breakthrough Fusion Technology that transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools. Fusion Technology enables you to accelerate the delivery of your designs with the industry-best full-flow QoR and the fastest time-to-results.

Keynote: Thinking Outside the CMOS Box

Abstract: “Even if the progression of Moore’s law continues relentlessly, in 2040 it would still take the world fastest supercomputer a billion years to factor RSA-2048, a 617-digit semiprime number, and the simulation of nitrogenase enzyme co-factor, a fairly simple organic molecule, would not be completed before the end of our universe.
Lagging microprocessor frequency, latency across the processor, memory, and storage stack, as well as the signal losses in electrical transmission lines prevent breakthrough improvements in performance and power efficiency.
The computing and memory requirements of artificial intelligence (AI), biochemistry, medicine, pharmacology, and physics applications greatly exceed the capabilities of current electronics and are unlikely to be met by isolated improvements in devices, or integrated circuit architectures alone.
Circuits based on super-conducting electronics (SCE) have made many advances in the last few years. Short term, Josephson junction-based SCE promises to invigorate HPC by delivering at least an order of magnitude more performance using 100X less power. Longer term, SCE is the best available foundation for a new class of computers, based on the laws of quantum physics, quantum computers (QC), which may dramatically change the landscape of HPC for problems that can be handled by this class of very different hardware.
Exascale computing demands for exascale bandwidth: silicon photonics is capable of dramatically faster data communications, at a much lower power, and can play a critical role as a link between the sub-4°K SCE/QC world and the room temperature (300°K), classical computing world.
Discrete and monolithic 3D-IC may help unleashing the full potential of heterogeneous integration of different functions – compute, store, sense/actuate – and could allow for their independent evolution, both w.r.t. the process technology and the design tools.
This talk offers an overview of the looming innovations that may change the landscape of our industry.”

Bringing Digital Intelligence to the Synopsys Design Platform

Machine learning (ML) is emerging as a powerful technology for addressing high-complexity, high-cost challenges across a multitude of applications in chip design. This presentation will discuss Synopsys approach to ML and illustrate examples of how this new, digital intelligence is making it possible to accelerate design turnaround and achieve optimal quality-of-results.

Front End Implementation

Synthesis, Low Power & FV 18.06 Update and Roadmap

In this section we will cover the  highlights of Design Compiler and Formality 2018.06 releases.
For synthesis, in particular improvements in QoR, and new features to support
advanced technology nodes will be presented. And for equivalency checking recent improvements
in verification completion will be covered along with many other enhancements.

Power Optimisation and PrimePower

In this session we will cover the 18.06 enhancements to the Galaxy Low Power Platform. This will include enhancements to IEEE1801 construct support, UPF implementation support and usability improvements.
This session will also cover changes in the Power Analysis space by covering detail of 18.06 next generation power analysis signoff product, PrimePower.


This session will also cover changes in the Power Analysis space by covering detail of 18.06 next generation power analysis signoff product, PrimePower

PrimeTime 18.06 Update and Roadmap

In this session we will cover highlights of the 2018.06 release of the PrimeTime® Suite. This will include an introduction to AI-enabled signoff-driven power recovery which, through machine-learning, is already demonstrating significant productivity increases in power recovery cycles. We will discuss advancements for ultra-low voltage threshold accuracy; significant performance improvements for reporting; and we’ll discuss a new, direct, PrimeTime – ANSYS Redhawk link. We will also introduce a new capability for access and exploration of your parasitic GPD databases for analysis and debug support. And of course we will touch on many other features and enhancement across the timing analysis and design closure space.

Place and Route Physical Implementation

Place and Route 18.06 Update and Roadmap

In this section we will look at a range of technology updates that have been incorporated into IC Compiler™ II.
For example we will review the evolution of our library to support our fusion platform through to additional tool support required for the challenges presented by the advanced nodes. These will include our advanced legalization engine, pin access optimization as well as our route driven estimation technology.

“Get it right!"  Accelerating Physical Signoff.

“Get it right!"  Accelerating Physical Signoff.
This session looks at using IC Validator ‘Explorer’ and ‘In-design’ as an
integral part of Implementation and as the complete Physical Verification
signoff solution for complex designs at advanced technology nodes.”

Redhawk Fusion

ICC2 RedHawk Analysis Fusion
Learn how IC Compiler™ II with RedHawk™ Analysis Fusion integration helps you not only analyse your power integrity, but also fix it.
• IC Compiler II with RedHawk Analysis Fusion is an integrated environment created for physical designers to do in-design rail analysis and repair
• Includes common analysis features such as connectivity checks and static and dynamic analysis coverage, with and without vectors
• Leverage automatic in-design rail fixing capabilities including PG augmentation and missing via insertion

IC Compiler™ II Design Planning Technology

Comprehensive Overview of the IC Compiler™ II Design Planning Flow and Technology
Learn how IC Compiler™ II Design Planning can efficiently get you to tape out with very large
hierarchical SoCs or just flat blocks. Technologies covered will include:
• Automatic block & voltage area shaping over multiple levels of physical hierarchy
• Tape out quality automatic macro placement with large numbers of macros.
• Multiply Instantiated Block (MIB) aware time budgeting, shaping & pin assignment.
• Black Box support including black box timing models.
• MIB aware pattern based power ground synthesis.
• Fast interactive GUI "what if" analysis and GUI based Task Assistant.

Functional Verification

Formal Techniques

VC Formal Tech Update 2018.09

A sneak peek into VC Formal (VCF) capabilities coming in 2018.09. This session outlines many recent enhancements in FPV, FTA, CC & FSV (VC Formal Apps). We will also be introducing Automatic Testcase Extraction (ATE) for VCF and the Data Path Verification app (DPV) in VC Formal that integrates Hector into VC Formal.

SpyGlass Update

Optimizing Performance and Debug of SpyGlass CDC/RDC
With increasing numbers of clock and reset domains in designs, and increasing design sizes, CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis continues to grow in importance. This session outlines many recent enhancements in the SpyGlass CDC/RDC environment targeted towards improving runtimes (both for full and incremental turnaround times) and for debugging the issues identified by the analysis”

Verdi-VCS 2018.09 Update

Simulation and Debug performance

Simulation and Debug– Make the most of the built-in technologies in VCS to improve compile and run time performance.
This session will go through hints and tips for best practises on improving simulation performance and Debug TAT
Users can learn more on simulation profiling, Pre compiled IP and Partition compile flow along with shortened Debug TAT using checkpoint and Reverse debug


While systemic complexity growth in automotive electronics is driving the need for comprehensive functional safety verification, fault injection testing remains a key element of ISO 26262 functional safety verification.
In this session, we will give an introduction to Synopsys’ functional safety verification solution, and highlight some of the features of Z01X, the fastest functional safety fault simulator in the industry.

Test Solutions and Automotive

SpyGlass DFT ADV for Improving Testability

This session expounds on some new benefits of SpyGlass® DFT ADV, including test points for untestable faults, and X-bounding analysis which are integrated with the physically-aware test point insertion flow. In addition, you will learn how to write custom DRCs to support your individual design methodologies using the connectivity checker.

Test Solution for Manufacturing Test and Functional Safety

TetraMAX® II, Synopsys' next-generation ATPG and diagnostics solution, addresses the ATPG runtime bottleneck, delivering an order of magnitude faster runtime with significantly fewer patterns than existing ATPG solutions. This session updates you on TetraMAX II successes and features and highlights several other key technologies in the Synopsys test platform such as DFTMAX™ compression and LogicBIST.

Cell-Aware Technology for Testing and Yield Analysis

This session updates you on features to improve defect detection and diagnostics well suited for FinFET. Topics include combined slack-based transition and cell-aware ATPG, multi-bit cell diagnostic support, and improved throughput using TetraMAX® II.

Custom and AMS

Large scale Monte Carlo analysis and data mining

As technology is scaled down further, at FinFET/advanced nodes, design variability has become prominent. The impact of process variation is particularly significant for FinFET designs because of their more complex manufacturing, lower supply voltages, as well as increased circuit complexity. Accurate analysis of design and process variations are required to give designers the confidence in the robustness of their chip. To ensure overall yield, it is important that designers validate these highly sensitive circuits for high sigma. However, achieving statistically valid results using traditional methods for such sigma extremes would require 10,000-100,000 MC iterations.
This tutorial will discuss how Synopsys simulators, along with foundry-certified device and statistical models, provide various advanced statistical analyses and sampling methods, together with a sigma scaling approach. These approaches can allow validation of designs to high sigma using far fewer MC samples.
Also discussed will be Custom Compiler's Simulation Analysis Environment (SAE), which provides an intuitive environment for MC simulation setup, powerful charting, data mining and results viewing capabilities, in order to significantly speed up and simplify the debugging process.

Delivering robust AMS designs

The growth in safety-critical applications for Automotive and the mainstream adoption of FinFET technologies have resulted in a significant increase in IC design challenges. Today's IC designers have to contend with a dual set of challenges: FinFET design complexity and stringent performance, safety, and reliability requirements demanded by these applications. In particular, Automotive IC designers working on safety-critical applications such as Autonomous Driving, ADAS, and Connected Car, are now looking to adopt rigorous and systematic methodologies to ensure functional safety and high reliability. In this presentation, we will highlight the latest advances in Synopsys' circuit simulation solutions to address these challenges and share Synopsys' perspective on analog fault simulation for functional safety and other emerging applications.

Custom Compiler, in-design EM analysis and parasitic estimation

Due to the higher current carrying capacity of FinFET's, Electromigration (EM) is becoming an increasingly important issue for analog designers at 16nm and below. It is no longer a problem limited to a few power- or clock-nets, but also signal nets need to be checked for EM. The Electrical Aware Design features of Custom Compiler is aimed at helping the analog designer to achieve an EM correct layout using as few layout iterations as possible. This includes using Custom Compilers pre-layout R&C planning and estimation during design analysis, using the terminal current data from simulation to drive the layout implementation, and finally to verify the EM correctness of the layout using the in-design EM reporting features.

Custom Compiler Template-Based Design for Layout Assistance

Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistants placer and router. They intelligently recognize circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler's Symbolic Editor, for example, comes pre-loaded with a set of built-in templates for commonly-used circuits, such as current mirrors, level-shifters and differential pairs.

Utilizing VCS AMS for High Performance Mixed Signal Verification

In this presentation we will review the advanced features available in VCS AMS that enable rapid verification of Mixed Signal Designs.
The tutorial will cover how significant efficiency gains can be made by using capabilities such as the VCS AMS real/nettype modelling flow, industry leading fastSPICE simulation and Save and Restore.
We will also show how VCS AMS enables the use of UPF in a mixed signal simulation so that the effect of low power strategies on the analog blocks in a design can be analyzed.

Analog debug - Custom WaveView Update

Custom WaveView updates and a tutorial on design debugging using DesignView.
This presentation will cover the new enhancements in, the Synopsys analog debug tool, Custom WaveView and spice debugging & connectivity tracing in DesignView. The following topics are included in this presentation.  Enhancements in Custom WaveView ACE-TCL measurement automation in Custom WaveView. DesignView capabilities. Connectivity tracing. Spice debugging Current debugging

Advanced electrical rule checking - Circuit check overview and update

Circuit Check offers advanced Electrical Rule Checking to quickly and efficiently find bugs in your design not otherwise detectable using conventional simulation tools.
With the ever increasing complexity of SOC designs and the requirements for lower power using multiple power domains, design errors can inadvertently be introduced due to leakage, missing level shifters, missing retention cells, forward-biasing bulk substrate diodes or missing ESD protection. Such errors can occur when multiple Power Domains in your design are switching on/off and can inadvertently switch on adjacent power domains, leading to excessive power consumption and reliability issues in the field. Therefore it's important to check your designs to ensure that none of these violations occur. It can be very difficult to detect these type of violations (eg, such floating gates, Hi-Z nodes, un-initialized latches, stuck-at nodes) using standard SPICE based simulation tools. CustomSim Circuit Check provides a comprehensive set of Static & Dynamic checks (ERC, Timing, SI) and API's for detecting these type of violations prior to tape out.