Synopsys Scandic Technology Symposiums 2018

Synopsys is hosting two Technical Symposiums focusing on critical aspects of doing state of the art designs at established and emerging nodes. 

The event provides an opportunity for users to stay connected with the latest Front End Implementation, Back End Implementation and Sign Off as well as getting tips & tricks and best practices that our experts will share. Experts will update you on exciting new technologies and features that are now available.

You will also have the opportunity to win an Amazon Echo Plus in the prize draw at the end of the day.

echo plus


Tuesday, 13th November
Scandic Copenhagen, Vester Søgade 6, DK-1601 Kobenhavn V. 


Thursday 15th November
Scandic Lerkendal, Klæbuveien 127, Trondheim 7031 Norway

If interested, you are welcome to move between tracks. The tracks commence at 09.00 a.m. with registration and refreshments from 8.30 a.m. To register click on the links above or visit:

Detailed Agenda

08:30-08:45      Registration and Beverages
08:45-09:00      Introduction
09:00-10:15     Synthesis & Formality 18.06 Update and Roadmap
10:15-10:30     Break
10:30-11:15     Galaxy Low Power (UPF) 18.06 update
11:15-12:00     SpyGlass DFT ADV for Improving Testability                
12:00-12:45     Lunch
12:45-14:15     Place and Route 18.06 Update and Roadmap(Martyn)
14:15-14:30     Break
14:30-15:00     PrimePower Introduction
15:00-16:15     PrimeTime 18.06 Update and Roadmap
16:15-16:30     Social and Prize Draw


Synthesis & FV 18.06 Update and Roadmap In this section we will cover the  highlights of Design Compiler and Formality 2018.06 releases.
For synthesis, in particular improvements in QoR, and new features to support
advanced technology nodes will be presented. And for equivalency checking recent improvements
in verification completion will be covered along with many other enhancements.
Galaxy Low Power (UPF) 18.06 Update In this session we will cover the 18.06 enhancements to the Galaxy Low Power Platform. This will include enhancements to IEEE1801 construct support, UPF implementation support and usability improvements.
SpyGlass DFT ADV for Improving Testability This session expounds on some new benefits of SpyGlass® DFT ADV, including test points for untestable faults, and X-bounding analysis which are integrated with the physically-aware test point insertion flow. In addition, you will learn how to write custom DRCs to support your individual design methodologies using the connectivity checker.
Place and Route 18.06 Update and Roadmap In this section we will look at a range of technology updates that have been incorporated into IC Compiler™ II.
For example we will review the evolution of our library to support our fusion platform through to additional tool support required for the challenges presented by the advanced nodes. These will include our advanced legalization engine, pin access optimization as well as our route driven estimation technology.
PrimePower Introduction This session will also cover changes in the Power Analysis space by covering detail of 18.06 next generation power analysis signoff
product, PrimePower
PrimeTime 18.06 Update and Roadmap In this session we will cover highlights of the 2018.06 release of the PrimeTime® Suite. This will include an introduction to AI-enabled signoff-driven power recovery which, through machine-learning, is already demonstrating significant productivity increases in power recovery cycles. We will discuss advancements for ultra-low voltage threshold accuracy; significant performance improvements for reporting; and we’ll discuss a new, direct, PrimeTime – ANSYS Redhawk link. We will also introduce a new capability for access and exploration of your parasitic GPD databases for analysis and debug support. And of course we will touch on many other features and enhancement across the timing analysis and design closure space.