Synopsys France Technology Symposium 2019

Synopsys is hosting a Technology Symposium focusing on critical aspects of doing state of the art designs at emerging and established nodes. This event provides an opportunity for users to stay connected with the latest products and innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share.

Synopsys technical experts will provide an “under the hood” look at proven and new technologies that designers can use to meet their aggressive time schedules and to achieve challenging Performance, Power and Area goals.

Multiple tracks will be offered where experts will update you on exciting new technologies and features that are now available.

We will conclude the day with a social event where you will have the opportunity to meet and discuss with your industry peers and Synopsys experts in an informal atmosphere

Date & Venue:

Wednesday, 27th November
World Trade Center, 5-7, Place Robert Schuman, 38000 GRENOBLE

9:00 a.m. – 6:00 p.m.

Registration starts at 9:00 a.m. The technical program will kick off at 10:00 a.m. with a keynote by TBD

To register, click on the link below or visit: http://events.synopsys.com.

Detailed Agenda - France

09:00 - 10:00
Registration and Refreshments
10:00 - 11:00
Welcome and Keynote
Keynote: Design in the Era of «Computer Humans»
Marco Casale-Rossi
- Product Marketing Manager, Office of the President, Synopsys
(Auditorium)
11:00 - 11:15
BREAK (Atrium)
Tracks/Rooms Implementation

Mont-Blanc 1
RTL Synthesis and Sign-off

Mont-Blanc 3
Test

Kilimandjaro 3
AMS

Cervin
Verification

Kilimandjaro 1
  A1 - IC Compiler II A2 - Timing ECO A3 - Optimize DFT for Better QoR A4 - VCS AMS Advanced Flow A5 - Dynamic Verification Update
11:15 - 12:15 IC Compiler II Update - Synopsys Latest Advances with PT-ADV: Accelerated Design Closure with PTECO - Synopsys Can DFTMAX Ultra Compression Results be Improved by Reducing the Effects of Decompressor Dependencies? - Dialog Semiconductor eSTM Flash Memory IP AMS Verification Strategy & Device Modelling Improvements - STMicroelectronics What's New in VCS and Verdi? - Synopsys
IC Compiler II Roadmap: Introducing Machine Learning - Synopsys PrimeECO Design Closure System - Synopsys Transition Fault Pattern Optimization for Mixed-Signal SOCs using Low-Power Budget Options - STMicroelectronics VCS-AMS UPF Mixed-Signal Flow for STMicroelectronics Bluetooth Low Energy Design Verifications  - STMicroelectronics
12:15 - 13:30
LUNCH (Atrium)
  B1 - In-Design Technologies B2 - RTL Synthesis and Functional Verification B3 - Test Pattern Validation and FC-DFT B4 - Advanced Flow and CustomSim Update B5 - Static Verification Update
13:30 - 15:00 IC Compiler II In-Design Technologies - Synopsys Design Compiler® NXT - Tutorial Covering Latest 2019.03-SPx Release Update - Synopsys MaxTB to Set Up  and VCS FGP to Speed Up Test Patterns Validation - Synopsys TestMax CustomFault on Automotive IP's - STMicroelectronics Machine Learning RCA Cutting Debug Time by 10X for Low Power and CDC Analysis - Synopsys
Formality and Formality ECO Update - Synopsys ATE Functional Patterns Coverage with Z01X - Synopsys AMS Update - Synopsys
How Do SpyGlass Constraints Help? - Synopsys
ST ODIF KIT Taking Benefit of ICCII/FC In-Design Technologies to Boost Design Implementation Productivity - STMicroelectronics Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs - Synopsys Introduction to Fusion Compiler DFT - Synopsys
15:00 - 15:30
BREAK (Atrium)
  C1 - Synopsys Fusion Compiler C2 - Signoff and Beyond C3 - TestMAX - All You Need to Know C4 - Analog Custom Implementation C5 - HW and Formal Verification
15:30 - 17:00  A Look Inside Fusion Compiler, its Technology Underpinnings and how this Next-Generation RTL-to-GDSII Solution is Natively Architected to Deliver Class-Leading QoR and Time-to-Results - Synopsys Introduction to PrimePower - Synopsys Synopsys TestMAX™ Family of Test Products - Overview - Synopsys CustomCompiler Ecosystem at STMicroelectronics - STMicroelectronics The State of the Play with HAPS Based FPGA Prototyping - Synopsys
Beyond Signoff: Parametric Yield Analysis - Synopsys Synopsys TestMAX™ Family of Test Products - TestMAX XLBIST - TestMAX FuSa - Synopsys Asynchronous Memory interface with Custom Design Flow - Tiempo
Formal to the Rescue for Safety and Security Applications - Synopsys
Fusion Compiler Customer Results - STMicroelectronics StarRC / Parasitics Explorer: Update and Introduction to Advanced Debug - Synopsys Complete Reliability Analysis and Effective Design/Layout Collaboration with Custom Compiler - Synopsys
17:00 - 18:00
SOCIAL EVENT (Atrium)

Abstracts:

Keynote

Design in the Era of «Computer Humans»

Abstract: Sixty years ago, Katherine G. Johnson worked at the NASA Langley Research Center “West Area Computing Unit”, where she and many other African American, female mathematicians acted as human computers to help win the space race. Today, thanks to the progress of computer hardware and software, vertical, application-specific artificial intelligence (AI) is almost ready for the primetime, and horizontal, general-purpose AI seems within our reach. Our journey brought us from “human [acting as] computers” to “computer [acting as] humans”. We are at the dawn of a new era: IoT – the Internet-of-Thing – is becoming AIoT – the Artificial-Intelligence-of-Things: ubiquitous, connected, autonomous, intelligent things. Amazing, isn’t it? But, potentially, also scary. A design paradigm shift is badly needed.

Over these sixty years, we have striven to improve PPA – performance, power, and area – design angles, often disregarding everything else. Moving forward, regardless of the application, there are another three critical design angles to be addressed: security, i.e. the protection of the system and the environment from humans; safety, i.e. the protection of humans and the environment from the system; and reliability, i.e. the protection of humans and the system from the environment (defects, faults, at any stage of the system lifespan). Always bearing in mind that, after Murphy’s Law – which is as important as Moore’s Law – “anything that can go wrong, will go wrong”: there ain’t such things as enough secure, enough safe, or enough reliable.

 

Implementation

IC Compiler II Update

Abstract: This tutorial provides an update on the latest design implementation technologies available in the IC Compiler II latest releases. The presentation includes highlight of the new features such as advanced node enablement and optimal out-of-the-box QoR to achieve best performance, power and area targets with fastest time to results. Attend this session to learn how to deploy these latest technological advancements in your physical implementation flow.

  • Synopsys Tools Used: IC Compiler II
  • Target Audience: All IC Compiler II users


IC Compiler II Roadmap: Introducing Machine Learning

Abstract: Please check back later for details

 

IC Compiler II In-Design Technologies

Abstract: The Synopsys Fusion Technology transforms the implementation flow, enabling industry-golden signoff tools within IC Compiler II environment, and accelerates the turn-around time of next-generation designs. This presentation will highlight technologies from the Synopsys Fusion Technology platform to fasten design closure:

  • It will provide details on the ECO Fusion technology that automates PrimeTime ECO design closure flow from within IC Compiler II environment.
  • It will also highlight IC Compiler II enhancements to perform IRDrop analysis and fixing using Ansys RedHawk, an industry standard power noise and reliability sign-off solution for SoC designs.
  • Finally, you will learn about the latest In-Design  IC Validator technology to enhance physical verification productivity across the full design flow.

 

ST ODIF KIT Taking Benefit of ICCII/FC In-Design Technologies to Boost Design Implementation Productivity

Abstract: Please check back later for details

 

A Look Inside Fusion Compiler, its Technology Underpinnings and how this Next-Generation RTL-to-GDSII Solution is Natively Architected to Deliver Class-Leading QoR and Time-to-Results

Abstract: In November 2018 Synopsys announced Fusion Compiler. Fusion Compiler is the only complete RTL to GDS tool, which enables it to deliver leading QoR and significant productivity improvements.
In this session we will provide an overview of what makes Fusion Compiler unique followed by a deep dive into the core technologies and common engines between synthesis and place-and-route domains to deliver the best performance, power, and area in the shortest time.

  • Synopsys Tools Used: Fusion Compiler

 

Fusion Compiler Customer Results

Abstract: Please check back later for details

RTL Synthesis and Sign-off

Latest Advances with PT-ADV: Accelerated Design Closure with PTECO

Abstract: This tutorial will provide an overview of the latest PrimeTime features and enhancements in the 2019.03 release which further raise the bar for the industry standard signoff solution. In addition to performance and capacity advances you will learn about new technologies such as Advanced Multiple Input Switching, high sigma critical path simulation, and via variation. We will also discuss advanced design closure technologies in PrimeTime ECO which help accelerate design closure and power recovery, offer better fixing rates and convergence.


PrimeECO Design Closure System

Abstract: This presentation introduces PrimeECO, a new Synopsys product that will be available in 2019.12. PrimeECO is a design closure system that performs fully incremental ECO implementation. It achieves signoff accurate and scalable multi-scenario coverage in a single cockpit using innovative hybrid-timing views architecture.

  • Synopsys Tools Used: PrimeECO


Design Compiler® NXT - Tutorial Covering Latest 2019.03-SPx Release Update

Abstract: Growing design complexity and new emerging nodes introduce new challenges that Design Compiler NXT can address.

It has many exciting new features and changes for the P-2019.03-SPx releases. This update training session explores these enhancements: Automotive, RC Correlation, NDM library Support, CCD optimization in early stages, and many more.

  • Synopsys Tools Used: Design Compiler NXT


Formality and Formality ECO Update

Abstract: In this section we will introduce our new Automatic ECO capabilities, review the interactive ECO features and provide updates for the latest releases of Formality.

This update will include enhancement to enable improved completion, new clock gating verification technology and additional debugging capabilities for both failing and hard verifications.


Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs

Abstract: System-on-chip (SoC) designers are implementing an increasing amount of functionality in software, to gain flexibility, mitigate against the uncertainty of supporting evolving standards, and to make it possible for a single chip to serve many end products.

Traditionally, designers had to choose between using an existing processor that is “close enough” to the required functionality, or reverting to the inflexibility of fixed-function hardware. A third option now available is to build an application-specific instruction-set processor (ASIP), whose instruction set and architecture is tailored to the needs of the target application. 

In this presentation we will explain how Synopsys’ ASIP Designer enables the efficient design, verification and programming of an ASIP. Its unique capability to rapidly generate a software development kit (SDK), and the tight integration of the hardware design process into Synopsys’ synthesis and verification flows significantly lower the barrier to adopt ASIPs for new design projects.


Introduction to PrimePower

Abstract: The introduction of PrimePower in 2018 was to ensure strong power analysis capability for next generation technologies and design flows. We'll review the latest enhancements and newest capabilities of PrimePower and how they specifically address these needs.

PrimePower is used within the implementation flow to guide decisions, target work, and measure progress on techniques to reduce design power. We'll introduce the needs and challenges for early-flow power, detail the flow that was developed, and review the quantitative results of their effort.

  • Synopsys Tools Used: PrimePower


Beyond Signoff: Parametric Yield Analysis

Abstract: In this workshop, we will present PrimeYield product, that enables post-STA design robustness and parametric yield analysis. We will concentrate specifically - on the critical path simulation, enabling Hspice MC simulation with practical turnaround time for any signoff flow, - on the robustness analysis which identifies cells with large process variation and with inadequate positive slack and - how the tool can adjust the path slacks to a desired target yield to address yield loss or high sigma sign-off problem.


StarRC / Parasitics Explorer: Update and Introduction to Advanced Debug

Abstract: In this tutorial we will introduce Parasitic Explorer in the starrc_shell. Parasitic Explorer is a multipurpose analysis/debug tool that enables the user to examine the details of the StarRC parasitic database (GPD). With Parasitic Explorer, users are able to query detailed information of every net in the design, create advanced parasitics-centric scripts and perform what-if analyses. Special visualization features are also available to examine interconnect topologies with annotated R and C values. Additional features and use examples will be shown to highlight the power of this environment.

We’ll also introduce Virtual Metal Fill 19.12 feature which enables designers to estimate the metal fill impact on timing faster and earlier in the design flow - and accelerate design closure dramatically. StarRC in-design & stand-alone VMF solution provides best-in-class correlation with real metal fill with a minimal performance foot-print.

Test

Can DFTMAX Ultra Compression Results be Improved by Reducing the Effects of Decompressor Dependencies?

Abstract: In any scan compression scheme the test coverage achieved is normally less than with uncompressed scan chains. This is due to the limitations of the decompressor and compressor blocks at the head/tail of the internal chains. Rules and guidelines already exist to limit these effects, such as placing OCC logic outside the compression scan chains or introducing X-chains. This paper looks at whether the initial organization and the reordering of the scan chains can be controlled to improve the test coverage by limiting the effects of the dependencies which exist between the data loaded into the chains.

  • Synopsys Tools Used: Design Compiler Graphical, DFTMAX Ultra, TetraMAX
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers


Transition Fault Pattern Optimization for Mixed-Signal SOCs using Low-Power Budget Options

Abstract: This presentation describes how ATPG Transition Fault patterns can be “power optimized” to fit in PrimeTime® signoff chip speed under min and max test conditions. We detail the “good compromise” for ATPG pattern generation depending on low power budget options and reducing patterns count. Using TetraMAX II, we prove that this can be done without test time impact on a complex mixed signal product, with huge SDC exceptions files, having a DFTMAX multi-compressor architecture. We conclude with silicon results and a comparison of TetraMAX II and TetraMAX performances on some products.

  • Synopsys Tools Used: DFTMAX, PrimeTime, TetraMAX, TetraMAX II
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers


MaxTB to Set Up and VCS FGP to Speed Up Test Patterns Validation

Abstract: Today’s designs have increased dramatically in size and complexity. With it have increased the challenges of completing DFT simulations in a timely fashion without delaying tapeout. Frequently, these simulations are the bottleneck to completing a project. This presentation covers first MaxTB the solution in TetraMAX to setup and prepare the simulation environment for the ATPG patterns. Then to address the need to accelerate these simulations, we present VCS Fine Grained Parallelism (FGP) the solution to achieve an order of magnitude in performance gain with performing the validation of the Test patterns.

  • Synopsys Tools Used: TestMAX ATPG, VCS, Verdi
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers


ATE Functional Patterns Coverage with Z01X

Abstract: With increasing fault/test coverage targets (e.g. FuSa, automotive applications), Z01X fault simulator can be used to complement/improve fault coverage by simulating and qualifying functional patterns and addressing some design styles that ATPG cannot handle, e.g. mixed-signal designs, blocks without full scan.

  • Synopsys Tools Used: TestMAX ATPG, Z01X, VCS
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers


Introduction to Fusion Compiler DFT

Abstract: In this tutorial you will learn how you can proceed with DFT insertion within Fusion Compiler. Fusion Compiler offers two possible flows:

  • DFT insertion at RTL (pre-compile) to achieve best PPA.
  • Traditional DFT insertion at gate level after initial compile.

    The tutorial will explain these two flows and their benefits.

  • Synopsys Tools Used: Fusion Compiler
  • Synopsys TestMAX Family of Test Products - Overview
     

Abstract: The Synopsys TestMAX™ family of products offers innovative, next-level test and diagnosis capabilities for all digital, memory and analog portions of a semiconductor device. This session will introduce the new comprehensive test automation solution spanning from early RTL validation right through to in-system test and diagnosis, integrated within the Synopsys Fusion Design Platform.

  • Synopsys Tools Used: TestMAX Family of Test Products
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers


Synopsys TestMAX Family of Test Products - TestMAX XLBIST - TestMAX FuSa

Abstract: For next coming applications, targeting automotive, medical and aerospace, designers are under increasing pressure to satisfy not only very high testability requirements, but also challenging functional safety requirements yet still meet aggressive time-to-market goals. This presentation will cover 2 critical technologies allowing to achieve this: TestMAX FuSa for early functional safety analysis to quickly identify best candidates for TMR and DCLS redundancy and estimate metrics for target ASILs level. And TestMAX XLBIST which is another key technology delivering efficient in-system self-test solution, mandatory in functional safety critical applications. This technology is industry's first X-tolerant architecture, resulting in smaller impact on test costs, faster time to market, and very high-performance level.

  • Synopsys Tools Used: TestMAX FuSa, TestMAX XLBIST, TestMAX ATPG
  • Target Audience: Implementation Engineers, DFT & Test Engineering, Technical Managers

 

AMS

eSTM Flash Memory IP AMS Verification Strategy & Device Modelling Improvements

Abstract: Flash memory IP is a complex block which contains both digital and analog parts, such as charge pumps and oscillators. Because of their relatively high operating frequency (can be above 100 MHz), they represent a huge cost in terms of simulation time, particularly for the erase operation. We propose a mixed mode simulation approach, based on XA-VCS to validate the Flash memory IP in a reasonable time with good level of precision. Flash bitcell modelling, as well as fast-spice tuning have been optimized, giving rise to huge runtime improvement.


VCS-AMS UPF Mixed-Signal Flow for STMicroelectronics Bluetooth Low Energy Design Verifications

Abstract: Digital on Top (DoT) strategy is more and more a standard in semi-conductor industry. Mixed-signal verifications have to be developed in digital verification environment.

New digital verification features must be supported for mixed signal verifications.  Some years ago, UPF (IEEE1801) has been introduced in RTL to GDS flow and is now a must for mixed signal verifications. In this presentation we will see, through a STMicroelectronics project, some aspects of VCS-AMS© UPF flow.


TestMax CustomFault on Automotive IP's

Abstract: The increasing complexity of the circuits due to the constant integration of new technologies presents new challenges for manufacturing test methodologies and analysis. This is especially true in some critical field like automotive due to the safety application requiring an efficient failure analysis in order to find a corrective action and evaluate the risk for a population with failure. This presentation will deal with the integration of the analog simulation in the normal failure analysis flow. In particular, we will show how the results can be used as support for the fault isolation step speeding up the whole analysis process. Starting from this new flow we will also show how CustomFault in our process is shortening the identification of failure through examples of failure analysis.


AMS Update

Abstract: Please check back later for details


CustomCompiler Ecosystem at STMicroelectronics

Abstract: Custom Compiler design framework is currently used by STMicroelectronics for the development of the core and IP libraries in many technologies. Although it provides many advanced features in nature, STMicroelectronics mixed-signal design flow requires to use several other internal or external tools. The aim of this paper is to show the progress that has been done since the project has started in 2015.

  • Firstly, other Synopsys tools like analog and mixed-signal simulators (Hspice, CustomSim, FineSim, VCS), interconnect parasitic extractor (StarRC) and place & route tools (ICC1, ICC2) communicates easily with Custom Compiler. STMicroelectronics and Synopsys R&D have collaborated to improve the setup of some tools like CustomSim-RA, StarRC and ICC1.
  • Secondly, STMicroelectronics and Synopsys R&D and several other EDA companies have worked together to create an ecosystem which is now production. The two main EDA companies that have been involved in this project are Mentor for analog and mixed-signal simulation and physical verification and Dassault for data management. Note that several other EDA companies provide tools that are integrated in Custom Compiler like MunEDA for circuit optimization.
  • Thirdly, STMicroelectronics and Synopsys R&D have collaborated to integrate ST internal tools like Spice model setup corners and library verification tools in the Custom Compiler platform in order to ease the adoption of the new framework by the ST designers.


Asynchronous Memory interface with Custom Design Flow

Abstract: With the most recent technologies and the growing complexity of the circuits it becomes very delicate to manage the build of the clocks trees.

Tiempo designs IPs that works without clock signal. These circuits are called « asynchronous ». In addition to their lighter conception they naturally offer advantages like the robustness to the corner parameters (supply voltage, temperature, process …). Tiempo has developed its own synthesis tool and libraries of cells dedicated to the asynchronous design. But Tiempo is also concerned about the wish to develop its IPs with the standard design tools.

For the Backend, from the build of the libraries to the full placement and route of the IPs, Tiempo has chosen the Synopsys tools for all the steps. Firstly, the flow of the generation of an asynchronous library is described.

The last part is a typical case of a customization of a memory block. An interface is added to a synchronous memory to get an IP compatible with the asynchronous protocol. The backend flow of this exercise is presented in this part.


Complete Reliability Analysis and Effective Design/Layout Collaboration with Custom Compiler

Abstract: In this tutorial you will hear about Custom Compiler design and layout collaboration.

At start we will discuss the early in-design electrical analysis including Resistance, Capacitance and EM early estimations. Followed by the introduction of the new CustomSim-RA Signoff EM assistant to expedite the flow setup, functionalities of result viewer which is fully integrated to the Layout allowing an easy validation, correction and what-if analysis. The tutorial will end with Custom Compiler Design Review Assistant. This new functionality is a modern design review allowing effective communication between global teams, knowledge transfer and more importantly directed feedback that doesn’t need multiple levels of communication.

Verification

What's New in VCS and Verdi

Abstract: An update on the new features and functionality present in the tool's latest release.

  • Synopsys Tools Used: VCS, Verdi
  • Target Audience: Verification engineers


Machine Learning RCA Cutting Debug Time by 10X For Low Power and CDC Analysis

Abstract: NexGen SoCs with advanced graphics, computing and Artificial intelligence capabilities are posing new unseen challenges in verification. Designers and verification engineers using static verification technologies like LP/CDC/RDC often complain about the large number of violations generated by these tools. Efficiently debugging and root-causing issues becomes a huge challenge. This tutorial will talk about the present application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for related group of violations. This will significantly help to reduce the overall TAT for verification closure ensuring a “shift-left” and also make sure that subtle bugs do not escape into silicon.

  • Synopsys Tools Used: VC SpyGlass CDC, VC LP


How Do SpyGlass Constraints Help?

Abstract: Validating constraints throughout the design flow requires a methodology that guides designers through each step in the flow, specifying how to clean up and optimize the design constraints. This not only improves the QoR but reduces expensive re-spins and iterations. SpyGlass Constraints product helps in checking for constraints completeness by identifying missing clock and IO constraints, checks for constraints redundancy and helps in setting up SDC for early CDC analysis. By using SpyGlass Constraints at the RTL level one can save cost by reducing the backend iterations significantly.

SpyGlass TxV solution checks for correctness of timing exceptions such as false paths and multi-cycle paths. If incorrect, these failures can lead to chip failure or re-spin. Hybrid flow enables the generation of System Verilog Assertions (SVA) which can be plugged into simulation and verified for functional correctness of these constraints.

  • Synopsys Tools Used: SpyGlass Constraints
  • Target Audience: Designers, Design Managers


The State of the Play with HAPS Based FPGA Prototyping

Abstract: With FPGA Based prototyping now an established Software Development and System Validation technology, the most recent focus has been on extending visibility techniques to enable more effective debug capabilities. This session will overview those latest techniques and some of the innovative ways they have been deployed to enable further adoption.

  • Synopsys Tools Used: HAPS, ProtoCompiler
  • Target Audience: Software Engineers, Designers, Technical Managers


Formal to the Rescue for Safety and Security Applications

Abstract: Mission critical systems need reliable software to tell you how your product will operate in the event of a crisis. VC Formal FUSA from Synopsys can stress test your designs by instrumenting faults in RTL and check if they propagate, if they are detected and if your design has managed to mitigate them. Make your designs functionally safe using Synopsys VC Formal.

  • Synopsys Tools Used: VC Formal