Latest Advances with PT-ADV: Accelerated Design Closure with PTECO
Abstract: This tutorial will provide an overview of the latest PrimeTime features and enhancements in the 2019.03 release which further raise the bar for the industry standard signoff solution. In addition to performance and capacity advances you will learn about new technologies such as Advanced Multiple Input Switching, high sigma critical path simulation, and via variation. We will also discuss advanced design closure technologies in PrimeTime ECO which help accelerate design closure and power recovery, offer better fixing rates and convergence.
PrimeECO Design Closure System
Abstract: This presentation introduces PrimeECO, a new Synopsys product that will be available in 2019.12. PrimeECO is a design closure system that performs fully incremental ECO implementation. It achieves signoff accurate and scalable multi-scenario coverage in a single cockpit using innovative hybrid-timing views architecture.
- Synopsys Tools Used: PrimeECO
Design Compiler® NXT - Tutorial Covering Latest 2019.03-SPx Release Update
Abstract: Growing design complexity and new emerging nodes introduce new challenges that Design Compiler NXT can address.
It has many exciting new features and changes for the P-2019.03-SPx releases. This update training session explores these enhancements: Automotive, RC Correlation, NDM library Support, CCD optimization in early stages, and many more.
- Synopsys Tools Used: Design Compiler NXT
Formality and Formality ECO Update
Abstract: In this section we will introduce our new Automatic ECO capabilities, review the interactive ECO features and provide updates for the latest releases of Formality.
This update will include enhancement to enable improved completion, new clock gating verification technology and additional debugging capabilities for both failing and hard verifications.
Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
Abstract: System-on-chip (SoC) designers are implementing an increasing amount of functionality in software, to gain flexibility, mitigate against the uncertainty of supporting evolving standards, and to make it possible for a single chip to serve many end products.
Traditionally, designers had to choose between using an existing processor that is “close enough” to the required functionality, or reverting to the inflexibility of fixed-function hardware. A third option now available is to build an application-specific instruction-set processor (ASIP), whose instruction set and architecture is tailored to the needs of the target application.
In this presentation we will explain how Synopsys’ ASIP Designer enables the efficient design, verification and programming of an ASIP. Its unique capability to rapidly generate a software development kit (SDK), and the tight integration of the hardware design process into Synopsys’ synthesis and verification flows significantly lower the barrier to adopt ASIPs for new design projects.
Introduction to PrimePower
Abstract: The introduction of PrimePower in 2018 was to ensure strong power analysis capability for next generation technologies and design flows. We'll review the latest enhancements and newest capabilities of PrimePower and how they specifically address these needs.
PrimePower is used within the implementation flow to guide decisions, target work, and measure progress on techniques to reduce design power. We'll introduce the needs and challenges for early-flow power, detail the flow that was developed, and review the quantitative results of their effort.
- Synopsys Tools Used: PrimePower
Beyond Signoff: Parametric Yield Analysis
Abstract: In this workshop, we will present PrimeYield product, that enables post-STA design robustness and parametric yield analysis. We will concentrate specifically - on the critical path simulation, enabling Hspice MC simulation with practical turnaround time for any signoff flow, - on the robustness analysis which identifies cells with large process variation and with inadequate positive slack and - how the tool can adjust the path slacks to a desired target yield to address yield loss or high sigma sign-off problem.
StarRC / Parasitics Explorer: Update and Introduction to Advanced Debug
Abstract: In this tutorial we will introduce Parasitic Explorer in the starrc_shell. Parasitic Explorer is a multipurpose analysis/debug tool that enables the user to examine the details of the StarRC parasitic database (GPD). With Parasitic Explorer, users are able to query detailed information of every net in the design, create advanced parasitics-centric scripts and perform what-if analyses. Special visualization features are also available to examine interconnect topologies with annotated R and C values. Additional features and use examples will be shown to highlight the power of this environment.
We’ll also introduce Virtual Metal Fill 19.12 feature which enables designers to estimate the metal fill impact on timing faster and earlier in the design flow - and accelerate design closure dramatically. StarRC in-design & stand-alone VMF solution provides best-in-class correlation with real metal fill with a minimal performance foot-print.