Synopsys Europe Technology Symposium 2019

Synopsys is hosting three Technical Symposiums focusing on critical aspects of doing state of the art designs at established and emerging nodes. 
This event provides an opportunity for users to stay connected with the latest Implementation and Verification updates and roadmaps as well as getting tips & tricks and best practices that our experts will share. Experts will update you on exciting new technologies and features that are now available.

You will also have the opportunity to win one of three $100 gift cards in the prize draw at the end of the day.

If interested, you are welcome to move between tracks. The tracks commence at 9.00am with registration and refreshments from 8.30am. To register click on the links above or visit: http://events.synopsys.com.

Detailed Agenda - Copenhagen, Trondheim

0830 - 0845
Registration and Beverages
  Implementation Verification
0845 - 0900 Introduction Introduction
0900 - 1015 Synthesis & Formality 19.03 Update and Roadmap Spyglass and Formal 19.06 Update and Roadmap
BREAK
1030 - 1115 Galaxy Low Power (UPF) 19.03 update Verification Planning Update
1115 - 1200 Synopsys TestMAX: Redefining Expectations for Test High Performance Simulation with VCS and Verdi - Update and Roadmap
LUNCH
1245 - 1345 ICCII Place and Route 19.03 Update and Roadmap RTL Verification and SW Bring Up with Emulation
1345-1445 Physical Signoff 19.03 Update and Roadmap  
BREAK
1500 - 1545 ECO Fusion and Roadmap Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
(Trondheim only)
1545 - 1630 PrimeTime 19.03 Update and Roadmap  
1630 - 1730
Social/Networking

DG

Introduction  
Synthesis & FV 19.03 Update and Roadmap Abstract: In this section we will Introduce next generation synthesis, Design Compiler NXT as well as Formality 2019.03 releases.
For synthesis, we willl cover enhancements in DC NXT to improve correlation to back-end, quicker time to results (TTR) and improves power, performance and area (PPA).
For equivalency checking we will cover recent license model changes, improvements
in verification completion with alternate strategies and details od additional changes in the low power verification space.
Galaxy Low Power (UPF) 19.03 Update Abstract: In this session we will cover the 19.03 enhancements to the Galaxy Low Power Platform. This will include enhancements to IEEE1801 construct support, UPF implementation support and usability improvements.
Synopsys TestMAX: Redefining Expectations for Test Abstract: The Synopsys TestMAX™ family of products offers innovative, next-level test and diagnosis capabilities for all digital, memory and analog portions of a semiconductor device. This session will give an introduction to the new comprehensive test automation solution spanning from early RTL validation right through to in-system test and diagnosis, integrated within the Synopsys Fusion Design Platform.
ICCII Place and Route 19.03 Update and Roadmap Abstract: 2019.03 IC Compiler II update
This session will review the latest features available in the IC Compiler II 2019.03 product update including related service packs.  The main topic areas covered:
• Power/Performance/Area (PPA) and Runtime Improvements
• Advanced technology node support
• Fusion technologies
 
We'll discuss a wide range of topics throughout the Place & Route flow and highlight how these latest technologies can assist the variety of goals typically faced by Physical Designer engineers.
ECO Fusion & Roadmap Abstract: This session will contrast ECO Fusion with PT-ECO illustrating the fundamental usage models and the added value  of ECO Fusion. It  will discuss the latest features before moving on to examining recommendations for best practice.
Case studies will be used to reinforce best practices and provide usage & debug tips to ECO Fusion users.
The presentation will conclude with a roadmap of upcoming features.
PrimeTime 19.03 Update and Roadmap Abstract: This session will introduce new features of the PrimeTime 2019.03 release including full flow performance improvements, enhanced ECO
techniques including simultaneous fixing techniques, TNS reduction, crosstalk minimization, and interactive physical ECO enhancements.
We will also introduce the newly announced PrimeYield product which is the industries fastest robustness, high-sigma and statistical yield
analysis and optimization solution. In addition we will highlight some exciting technologies from the Synopsys signoff roadmap.
Physical Signoff 19.03 Update and Roadmap Abstract: This session will provide and update of the latest IC Validator enhancements and will outline how productivity can be improved. Enhancements have also been made to the StarRC family and these will also be discussed

SG

Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs Abstract: System-on-chip (SoC) designers are implementing an increasing amount of functionality in software, to gain flexibility, mitigate against the uncertainty of supporting evolving standards, and to make it possible for a single chip to serve many end products. Traditionally, designers had to choose between using an existing processor that is “close enough” to the required functionality, or reverting to the inflexibility of fixed-function hardware. A third option now available is to build an application-specific instruction-set processor (ASIP), whose instruction set and architecture is tailored to the needs of the target application. In this presentation we will explain how Synopsys’ ASIP Designer enables the efficient design, verification and programming of an ASIP. Its unique capability to rapidly generate a software development kit (SDK), and the tight integration of the hardware design process into Synopsys’ synthesis and verification flows significantly lower the barrier to adopt ASIPs for new design projects. 

VG

Spyglass and Formal 19.06 Update and Roadmap Abstract: In this section, we will provide updates and roadmaps on Synopsys static verification tools such as Spyglass and VC Formal. We will show how state of the art machine learning techniques can be used with these tools to dramatically reduce debug time.
Verification Planning Update Abstract: We will describe how Synopsys verification tools help plan, execute and track a verification project through its lifecycle, from specs to tapeout. We will introduce the latest innovations in Verdi Planner and Execution Manager, as well as sharing some insights into how to efficiently generate, store and merge verification metrics from different sources.
High Performance Simulation with VCS and Verdi - Update and Roadmap Abstract: We will provide an overview of the latest developments in VCS and Verdi, that will include recent innovations in performance, AMS, low power and links to prototyping. We will show how to use VCS to ensure regressions are fully optimized, and some debug tricks and techniques unique to Verdi.  
RTL Verification and SW Bring Up with Emulation Abstract: In this section we will present our verification continuum. First testbench reuse with HW acceleration will be introduced, then high performance transaction-based emulation will be covered. Finally prototyping will be covered to address SW verification needs and real-IOs. A few other topics such as fault-injection, power estimation and hybrid emulation will also be highlighted

Detailed Agenda - Oulu

0830 - 0845
Registration and Beverages
  DG VG
0845 - 1000 Synthesis & Formality 19.03 Update and Roadmap Spyglass and Formal 19.06 - Update and Roadmap
High-Performance Simulation with VCS - Update and Roadmap
1000 - 1100 Galaxy Low Power (UPF) and Power Analysis update
Break
 
Break
RTL Verification and Software Bring-up with Emulation
1115 - 1200 Synopsys TestMAX: Redefining Expectations for Test
1200-1245
Lunch Service
1245-1430
Social / Networking

DG

Introduction  
Synthesis & FV 19.03 Update and Roadmap Abstract: In this section we will Introduce next generation synthesis, Design Compiler NXT as well as Formality 2019.03 releases.
For synthesis, we willl cover enhancements in DC NXT to improve correlation to back-end, quicker time to results (TTR) and improves power, performance and area (PPA).
For equivalency checking we will cover recent license model changes, improvements
in verification completion with alternate strategies and details od additional changes in the low power verification space.
Galaxy Low Power (UPF) and Power Analysis update Abstract: In this session we will cover the 19.03 enhancements to the Galaxy Low Power Platform. This will include enhancements to IEEE1801 construct support, UPF implementation support and usability improvements.
We will also give an overview of PrimePower, out latest power analysis tool. This will include useful 19.03 enhancements.
Synopsys TestMAX: Redefining Expectations for Test Abstract: The Synopsys TestMAX™ family of products offers innovative, next-level test and diagnosis capabilities for all digital, memory and analog portions of a semiconductor device. This session will give an introduction to the new comprehensive test automation solution spanning from early RTL validation right through to in-system test and diagnosis, integrated within the Synopsys Fusion Design Platform.

VG

Spyglass and Formal 19.06 - Update and Roadmap Abstract: In this section, we will provide updates and roadmaps on Synopsys static verification tools such as Spyglass and VC Formal. We will show how state of the art machine learning techniques can be used with these tools to dramatically reduce debug time.
High-Performance Simulation with VCS - Update and Roadmap Abstract: We will provide an overview of the latest developments in VCS and Verdi, that will include recent innovations in performance, AMS, low power and links to prototyping. We will show how to use VCS to ensure regressions are fully optimized, and some debug tricks and techniques unique to Verdi.  
RTL Verification and Software Bring-Up with Emulation Abstract: In this section we will present our verification continuum. First testbench reuse with HW acceleration will be introduced, then high performance transaction-based emulation will be covered. Finally prototyping will be covered to address SW verification needs and real-IOs. A few other topics such as fault-injection, power estimation and hybrid emulation will also be highlighted