Synopsys Conference Sessions

Wednesday, June 27

SESSION 42.6:

Convergence Techniques for C vs. RTL Equivalence Checking

Track: EDA, DESIGN
Time: 10:30 a.m. to 12:00 p.m.
Location: Room 2012

Formal Verification continues to be an increasingly important toolkit for a variety of design and validation tasks. In this session we will explore formal techniques related to timing, firmware, high-level synthesis, and general validation tasks.

Speaker:

Xiuxhan Feng, Samsung Austin R&D Center, Austin, TX

Authors:

Xiuxhan Feng, Samsung Austin R&D Center, Austin, TX
Li You, Samsung Austin R&D Center, Austin, TX
Rachna Nambiar Jain, Samsung Austin R&D Center, Austin, TX
Yong Liu, Synopsys, Mountain View, CA

 

SESSION 51:

New Directions in Simulation and Formal

Track: EDA, DESIGN
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 2012

Simulation continues to be an important part of the design and validation process. In this session, we will explore a variety of techniques that combine simulation with formal verification, relating to high-level modeling, functional safety, and synchronization issues. We will also present other advanced simulation techniques, addressing tricky coverage closure and asynchronous design issues.

Chair:

Ravindra Aneja, Synopsys, Mountain View, CA

SESSION 52:

Power Management Through the Tool Chain

Track: EDA, DESIGN
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 2010

Complex power management in today’s SOC low-power ASIC design affects Implementation, Verification, and Signoff aspects. Historically each of these were independent tasks with little inter-dependencies and risks. With the complex low power techniques used by designers, these flows need to work together in delivering a risk free solution with faster turn-around time (TAT).  This session of industry design experts will offer differing opinions on what is needed to achieve a coherent Low Power Solution, and also look into new requirements/strategies to address growing power demands at lower geometries 7nm and below.

Organizer:

Renu Mehra, Synopsys, San Jose, CA

SESSION 52.2:

Low Power Flow/Methodology

Track: DESIGN, IP
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 2010

Complex power management in today’s SOC low-power ASIC design affects Implementation, Verification, and Signoff aspects. Historically each of these were independent tasks with little inter-dependencies and risks. With the complex low power techniques used by designers, these flows need to work together in delivering a risk free solution with faster turn-around time (TAT).  This session of industry design experts will offer differing opinions on what is needed to achieve a coherent Low Power Solution, and also look into new requirements/strategies to address growing power demands at lower geometries 7nm and below.

Speaker:

Godwin Maben, Synopsys, San Jose, CA

Author:

Godwin Maben, Synopsys, San Jose, CA

POSTER SESSION 125.4:

Standard Cell EM Sign-off in SoC

Track: DESIGN, IP
Time: 5:00 p.m. to 6:00 p.m.
Location: Level 2 Exhibit Floor

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

            Qiuling Zeng, HiSilicon, Shanghai, China

Authors:

            Qiuling Zeng, HiSilicon, Shanghai, China
            Jie Cheng, ANSYS & HiSilicon, Shanghai, China
            James Chuang, Synopsys, Mountain View, CA

POSTER SESSION 125.9:

Comprehensive Connectivity Verification

Track: DESIGN, IP
Time: 5:00 p.m. to 6:00 p.m.
Location: Level 2 Exhibit Floor

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

            Joseph D'Errico, Cavium, Marlborough, MA

Authors:

            Shahid Ikram, Cavium, Marlborough, MA
            Joseph D'Errico, Cavium, Marlborough, MA
            Yasmin Farhan, Cavium, Marlborough, MA
            Jim Ellis, Cavium, Marlborough, MA
            Tushar Parikh, Synopsys, Marlborough, MA

POSTER SESSION 125.12:

Challenges in Clock and Reset Domain-Crossing Verification and Scalable Solutions

Track: DESIGN, IP
Time: 5:00 p.m. to 6:00 p.m.
Location: Level 2 Exhibit Floor

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

            Ashish Kumar Gupta, Broadcom, Bangalore, India

Authors:

            Ashish Kumar Gupta, Broadcom, Bangalore, India
            Anup Kumar Gupta, Synopsys, Bangalore, India

POSTER SESSION 125.22:

ISO26262-Compliant Soft-Error-Tolerant Design Methodology

Track: DESIGN, IP
Time: 5:00 p.m. to 6:00 p.m.
Location: Level 2 Exhibit Floor

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

            Akio Hirata, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan

Authors:

            Akio Hirata, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan
            Taizo Murakami, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan
            Hiromasa Fukazawa, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan
            Kazuyuki Nakanishi, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan
            Akinori Shibayama, Panasonic Industrial Devices Systems & Technology, Nagaokakyo City, Japan
            Abhishek Chauhan, Synopsys, Mountain View, CA
            Fadi Maamari, Synopsys, Mountain View, CA

Exhibit Hours

Mon: 10:00 a.m.– 6:00 p.m.
Tue: 10:00 a.m.– 6:00 p.m.
Wed: 10:00 a.m.– 6:00 p.m.