Synopsys Conference Sessions

Tuesday, June 26

SESSION 21.1:

A General Graph-based Pessimism Reduction Framework for Design Optimization of Timing Closure

Track: EDA
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 3018

Timing remains an essential challenge in digital design. To address it, the first paper brings a novel approximate path-based estimation model into a graph-based analysis framework; the second paper considers logic wave optimizations to optimally remove flip-flops while maintaining timing constraints. The third paper seeks to minimize the impact of DVFS sequence on power supply noise by optimizing the transition sequence of clock skipping and clock domain scheduling. Finally, the final paper develops an accurate wirelength distribution model which captures the physical aspects and the design-constraints of the system.

Speaker:

Fulin Peng, Fudan University, Shanghai, China

Authors:

Fulin Peng, Fudan University, Shanghai, China
Changhao Yan, Fudan University, Shanghai, China
Chunyang Feng, Synopsys, Shanghai, China
Jianquan Zheng, Synopsys, Shanghai, China
Sheng-Guo Wang, University of North Carolina, Charlotte, NC
Dian Zhou, Fudan University & University of Texas at Dallas, TX
Xuan Zeng, Fudan University, Shanghai, China

SESSION 24.3:

Machine Learning Opportunities in Design Automation

Track: EDA, DESIGN
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 3024

Today’s IC design process faces a crisis of cost and risk. Both human cost (i.e., engineering expertise and effort) and schedule cost (i.e., design schedule) are barriers to leading-edge design. This crisis has spurred new research initiatives that seek to substantially reduce the cost of IC design, even to unprecedented “no-human-in-the-loop” and 24-hour turnaround time levels. This session covers technical aspects of RTL-to-GDSII design effort reduction at the leading edge of EDA and design practice--today and in the future.

The session concludes with an EDA vendor perspective on opportunities and proof points for how EDA will enable design effort reductions for customers.

Speaker/Author:

Mayukh Bhattacharya, Synopsys, Mountain View, CA

SESSION 31.3:

Canonical Computation Without Canonical Representation

Track: EDA
Time: 3:30 p.m. to 5:30 p.m.
Location: Room 3022

Advancing the state of the art in approximate circuit synthesis.

Speaker:

Alan Mishchenko, University of California, Berkeley, CA

Authors:

            Alan Mishchenko, University of California, Berkeley, CA
            Robert K. Brayton, University of California, Berkeley, CA
            Ana Petkovska, École Polytechnique Fédérale de Lausanne, Switzerland
            Mathias Soeken, École Polytechnique Fédérale de Lausanne, Switzerland
            Luca Amarù, Synopsys, Sunnyvale, CA
            Antun Domic, Synopsys, Mountain View, CA

SESSION 34.4:

A Bottom-up Methodology to Evaluate Silicon Power Consumption for a Large Number of Application-Specific Scenarios

Track: EDA, DESIGN
Time: 3:30 p.m. to 5:00 p.m.
Location: Room 2010

Power and performance continue to be key concerns throughout the design flow, from architecture down to circuits. In this session we will explore some front-end techniques for improving power and performance, as well as seeing their application in a neural network design.

Speaker:

Vishwajith Singh, Synopsys, Mountain View, CA

Authors:

            Gur Samrao, Broadcom, San Jose, CA
            Vishwajith Singh, Synopsys, Mountain View, CA

POSTER SESSION 124.20:

A Novice's Experience with Formal Connectivity Check: Visibility, Capacity, Performance, Debug, and Closure

Track: DESIGN, IP
Time: 5:00 p.m. to 6:00 p.m.
Location: Level 2 Exhibit Floor

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

Nilesh Sonara, Broadcom, San Diego, CA

Authors:

            Nilesh Sonara, Broadcom, San Diego, CA
            Amir M. Nilipour, Synopsys, San Diego, CA
            Xiaolin Chen, Synopsys, Mountain View, CA

POSTER SESSION 120.42:

Size Optimization of MIGs with an Application to QCA and STMG Technologies

Track: WORK-IN-PROGRESS
Time: 6:00 p.m. to 7:00 p.m.
Location: Level 2 Lobby

During the poster presentation, you will interact directly with poster presenters in a small group setting.

Speaker:

Heinz Riener, École Polytechnique Fédérale de Lausanne, Switzerland

Authors:

            Heinz Riener, École Polytechnique Fédérale de Lausanne, Switzerland
            Eleonora Testa, École Polytechnique Fédérale de Lausanne, Switzerland
            Luca Amarù, Synopsys, Sunnyvale, CA
            Mathias Soeken, École Polytechnique Fédérale de Lausanne, Switzerland
            Giovanni De Micheli, École Polytechnique Fédérale de Lausanne, Switzerland

Exhibit Hours

Mon: 10:00 a.m.– 6:00 p.m.
Tue: 10:00 a.m.– 6:00 p.m.
Wed: 10:00 a.m.– 6:00 p.m.