Synopsys Conference Sessions

Thursday, June 28

SESSION 68:

Enhancing Manufacturability and Reliability in Advanced Technology Nodes

Track: EDA
Time: 10:30 a.m. to 12:00 p.m.
Location: Room 3024

This session presents assessments and new analysis techniques for yield, reliability and mask optimisations for advanced technology nodes. The first paper uses a GAN neural network to accelerate mask optimization. The second paper presents a Bayesian model for dimensionality reduction for fast estimation of SRAM failure regions. The third paper proposes compact models for interconnect aging including electromigration, thermomigration and stress migration. The last paper presents a sampling methodology for searching failure regions with reduced sample size and better efficiency and accuracy.

Chair:

Charles Chiang, Synopsys, Mountain View, CA

Co-Chair:

Evangeline F.Y. Young, Chinese University of Hong Kong, Hong Kong, China

SESSION 78:

Is It About Time to Take Inductance and Electromagnetic Effects on SoCs Seriously?

Track: EDA, DESIGN
Time: 3:30 p.m. to 4:25 p.m.
Location: Room 3020

Many experts argue that increased integration of complex high-speed digital, analog, and RF IP blocks within SoC designs has created new opportunities for electromagnetic (EM) crosstalk that we have traditionally ignored (both inside these complex IP blocks as well as across various blocks). And that the impact of crosstalk can be further exacerbated by the decrease in signal voltage levels driven by lower-power trends in today’s SoC applications. Other experts argue that internally-created EM crosstalk is important in analog design but is less of an issue with today’s large mixed-signal SoC designs. Furthermore, RC extraction engines are doing a good job of managing this problem, as well as adding margins to tolerate the impact on timing/power is working. This panel of experts will debate the following questions: Is internally-created SoC EM crosstalk a real issue today? Is inductance modeling required or not for advanced mixed-signal SoC designs? Can we continue to ignore inductance and rely on adding margins to tolerate the impact on timing, noise, etc.? And at what technology/frequency should we be worried? Do we need a sign-off methodology for EM crosstalk on all future advanced SoCs?

Panelists:

Ron Ho, Intel, San Jose, CA
Vishnu Balan, NVIDIA, Santa Clara, CA
Bari Biswas, Synopsys, Mountain View, CA
Pierre-Emmanuel Gaillardon, Univ. of Utah, Salt Lake City, UT
Luca Amaru, Synopsys, Mountain View, CA

Exhibit Hours

Mon: 10:00 a.m.– 6:00 p.m.
Tue: 10:00 a.m.– 6:00 p.m.
Wed: 10:00 a.m.– 6:00 p.m.