Synopsys Conference Sessions

Monday, June 25

SESSION 3:

Hardware IP for Deep Learning

Track: IP
Time: 10:30 a.m. to 12:00 p.m.
Location: Room 2008

The market for deep learning applications is predicted to grow at a 65% annual rate in the next 5 years. The growth is fueled by innovative hardware architectures that bring artificial intelligence to devices at the edge of the internet and at its core. Examples include voice assistants, face-based authentication, big data analytics and self-driving vehicles. Established companies as well as numerous semiconductor startups are introducing a diverse range of deep learning IP, and no winner has been declared yet. In this invited session players from industry and academics present their architecture, with programming examples and applications.

Chair:

Paul Stravers, Synopsys, Eindhoven, The Netherlands

TUTORIAL 8:

Machine Learning for EDA Applications

Track: MACHINE LEARNING/AI, EDA
Time: 1:30 p.m. to 5:00 p.m.
Location: Room 3020

This tutorial covers machine learning algorithms and application methodologies necessary for building EDA applications and flows. We discuss several unsupervised learning algorithms and some recent machine learning advances such as Generative Adversarial Networks which learn underlying data distributions without labels. Another class of problems we discuss involves systems or software agents that take actions in an environment to maximize some notion of cumulative reward. The problems in this class range from autonomous driving to driving randomized simulation for better coverage, to smart place and route algorithms. 
 
The second part of the tutorial focuses on the more practical aspects of applying different algorithms to solve classical EDA problems.

Speakers:

Manish Pandey, Synopsys, Mountain View, CA
Claudionor Coelho, Google, Mountain View, CA
Jeff Dyck, Mentor, Saskatoon, SK, Canada

SESSION 9.2:

Repair and Reliability Considerations for FinFET Memory IP

Track: IP, DESIGN
Time: 3:30 p.m. to 5:00 p.m.
Location: Room 2008

Achieving good testability and yield is often considered a problem that needs to be addressed at the IP level. However, system complexity, a heterogeneous IP portfolio, new technology constraints and the need to balance die size, performance and test cost also make it necessary to look at this problem from a SoC architecture and IP integration point of view. The presentations in this session sample some of the angles from which the issue can be addressed.

Speaker:

Raymond Leung, Synopsys, Mountain View, CA

Exhibit Hours

Mon: 10:00 a.m.– 6:00 p.m.
Tue: 10:00 a.m.– 6:00 p.m.
Wed: 10:00 a.m.– 6:00 p.m.